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Past Exam 1 with Answers - Advanced VLSI Design and Applications | ECEN 6263, Exams of Electrical and Electronics Engineering

Material Type: Exam; Professor: Johnson; Class: ADV VLSI DES & APP; Subject: Electrical and Computer Engineering ; University: Oklahoma State University - Stillwater; Term: Fall 2001;

Typology: Exams

2010/2011

Uploaded on 07/17/2011

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Download Past Exam 1 with Answers - Advanced VLSI Design and Applications | ECEN 6263 and more Exams Electrical and Electronics Engineering in PDF only on Docsity! ECEN 6263 Fall 2001 Exam 1 WRITE YOUR NAME HERE __ An Sw-0~ All questions must be answered on test paper! Open Book, Open Notes 1. Suppose a certain process has the following parameters. Rqj = 2882, Ry * 5KG2 Ry) = 9KQ, Ry, * 4KQ £ = 0.8m A 4 bus pair static RAM memory cell designed in this process is found to have the fol- lowing capacitive load on the bit line for each memory ceil attached to the bit line. Coit’ Newits = 208F +3(8F/um )Fapass Find the transistor widths Wyeei Wncetts ¥ npass for the 4 bus pair static RAM subject to the following constraints. + Tor each transistor 3pm < W<32pm. « The read access delay should be as small as possible. Well wy Ba Wo Vyey, w, $ as ‘dd - Wav = R : ms Eas | Tt ™. 2 * 422232 Wet zr , : Wa past § pu Vay. = R Ripusd Grva Read asesss miner )2el bow . . neell Wa pets AS bs As pusndle PR Lb - y mee EE) od —| s_ — | S&L Zott } Rawr Cymer awed -(& <n Maat lam) tn; w . id Ps: m f 3h “a needl> 32 sam ) A pase.= V 20230 am - 43 . * AS: Me Any Wpeuth <3 an 1F 6K ‘BCEN 6263 Fall 2001 Exam | ‘October 4, 2001 . vo : 2. Estimate the delays and power consumption im the circuit below using the RC model developed in class including the effects of the transistor threshold voltages V7, and Vyp. Use as parameters the channel sheet resistances and the widths of the six transis- tors, W;, ..., Wg, and the node capacitances, C;, .... C4. You may assume that the capac- ‘itances already contain all parasitics from the transistors and interconnect. a See ee yn eee tomowe: Tnitial voltage across C;?. Va ~ Vig tn , \ Final voltage across C)?__Q . . Initial voltage across C5? Vay : / 2 by ay Final voltage across C2?__ 0 Initial voltage across C;?__O . | ny, Final voltage across C37. @. 4 ra 2, 7 % Initial voltage across Cy?__O tf , v Final voltage across C4?__ Vad 1 | " “L o G: Delay from A to X? Rash oa T$ 4 ‘ Wok “one = Fu ¢ 1 ar) + 18L\ovy We, t ME TG Yip “fame Delay from A to Y? Et py = bsax + ey xy Va fiw = Rs GV a Wh 4s 1 . / Wy bay Rn “Wy a hat. Raf Reg ¢ avs eo ticks fata Pablla + He BCEN 6263 Fall 2001 Exam | ‘Genober 4, 2001 2
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