Pipelined MIPS Processor - Computer Architecture - Lecture Slides, Slides of Computer Science

Download Pipelined MIPS Processor - Computer Architecture - Lecture Slides and more Slides Computer Science in PDF only on Docsity! Arithmetic I CPSC 350 Docsity.com What happened so far? • We learned the basics of the MIPS assembly language • We briefly touched upon the translation to machine language • We formulated our goal, namely the implementation of a MIPS processor. Docsity.com Pipelined MIPS Processor We concentrate first on the arithmetic-logic unit Docsity.com The Arithmetic-Logic Unit • Arithmetic (addition and subtraction) – we need to know number representations – there exist various interesting algorithms for addition and subtraction – integer and floating point arithmetic • Logical operations (and, or, not) Docsity.com Computer Arithmetic Docsity.com Number representations What signed integer number representations do you know? Docsity.com Signed Numbers • Sign-magnitude representation – MSB represents sign, 31bits for magnitude • One’s complement – Use 0..231-1 for non-negative range – Invert all bits for negative numbers • Two’s complement – Same as one’s complement except – negative numbers are obtained by inverting all bits and adding 1 Docsity.com One’s Complement Suppose we want to express -30 as an 8bit integer in one’s complement representation. 30 = 0001 11102 Invert the bits to obtain the negative number: -30 = 1110 00012 Docsity.com Signed Numbers (3bits) sign magnitude one’s complement two’s complement 0002 = 0 0002 = 0 0002 = 0 0012 = 1 0012 = 1 0012 = 1 0102 = 2 0102 = 2 0102 = 2 0112 = 3 0112 = 3 0112 = 3 1002 = -0 1002 = -3 1002 = -4 1012 = -1 1012 = -2 1012 = -3 1102 = -2 1102 = -1 1102 = -2 1112 = -3 1112 = -0 1112 = -1 Docsity.com Two’s complement • The unsigned sum of an n-bit number and its negative yields? • Example with 3 bits: – 0112 – 1012 – 10002 = 2n => negate(x) = 2n-x • Explain one’s complement Docsity.com MIPS 32bit signed numbers 0000 0000 0000 0000 0000 0000 0000 0000two = 0ten 0000 0000 0000 0000 0000 0000 0000 0001two = +1ten 0000 0000 0000 0000 0000 0000 0000 0010two = +2ten ... 0111 1111 1111 1111 1111 1111 1111 1110two = +2,147,483,646ten 0111 1111 1111 1111 1111 1111 1111 1111two = +2,147,483,647ten 1000 0000 0000 0000 0000 0000 0000 0000two = –2,147,483,648ten 1000 0000 0000 0000 0000 0000 0000 0001two = –2,147,483,647ten 1000 0000 0000 0000 0000 0000 0000 0010two = –2,147,483,646ten ... 1111 1111 1111 1111 1111 1111 1111 1101two = –3ten 1111 1111 1111 1111 1111 1111 1111 1110two = –2ten 1111 1111 1111 1111 1111 1111 1111 1111two = –1ten Docsity.com Comparisons What can go wrong if you accidentally compare unsigned with signed numbers? Docsity.com Comparisons for [un]signed • Register $s0 – 1111 1111 1111 1111 1111 1111 1111 1111 • Register $s1 – 0000 0000 0000 0000 0000 0000 0000 0001 • Compare registers (set less than) – slt $t0, $s0, $s1 true, since –1 < 1 – sltu $t1, $s0, $s1 false, since 232-1>1 Docsity.com Addition & Subtraction • Just like in grade school (carry/borrow 1s) 0111 0111 0110 + 0110 - 0110 - 0101 1101 0001 0001 • Two's complement operations are simple – subtraction using addition of negative numbers 0111 = 7 + 1010 = -6 0001 Docsity.com Detecting Overflow • No overflow when adding a positive and a negative number • No overflow when signs are the same for subtraction • Overflow occurs when the value affects the sign: – overflow when adding two positives yields a negative – or, adding two negatives gives a positive – or, subtract a negative from a positive and get a negative – or, subtract a positive from a negative and get a positive Docsity.com Detecting Overflow Operation Operand A Operand B Overflow if result A+B >=0 >=0 <0 A+B <0 <0 >=0 A-B >=0 <0 <0 A-B <0 >=0 >=0 Docsity.com Effects of Overflow • An exception (interrupt) occurs – Control jumps to predefined address for exception – Interrupted address is saved for possible resumption • Don't always want to detect overflow – MIPS instructions: addu, addiu, subu note: addiu still sign-extends! Docsity.com Logic Gates: OR a b c 0 0 0 0 1 1 1 0 1 1 1 1 a b c Docsity.com An ALU (arithmetic logic unit) • Let's build an ALU to support the andi and ori instructions – Selection of operation 0 = and, 1 = or – we'll just build a 1 bit ALU, and use 32 of them • Possible Implementation (sum-of-products): b a operation result Docsity.com The Multiplexor • Selects one of the inputs to be the output, based on a control input • Build (and/or) ALU using a MUX S C A B 0 1 note: it is called a 2-input mux even though it has 3 inputs! Docsity.com Building a 32 bit ALU Result31 a31 b31 Result0 CarryIn a0 b0 Result1 a1 b1 Result2 a2 b2 Operation ALU0 CarryIn CarryOut ALU1 CarryIn CarryOut ALU2 CarryIn CarryOut ALU31 CarryIn b 0 2 Result Operation a 1 CarryIn CarryOut Docsity.com What about subtraction (a – b) ? • Two's complement approach: just negate b and add. • How do we negate? • A solution: 0 2 Result Operation a 1 CarryIn CarryOut 0 1 Binvert b Docsity.com