Pipelined Processor - Computer Architecture and Design - Lecture Slides, Slides of Computer Science

Download Pipelined Processor - Computer Architecture and Design - Lecture Slides and more Slides Computer Science in PDF only on Docsity! Page 1 1chapter 6 Designing a Pipelined Processor In this Chapter, we will study 1. Pipelined datapath 2. Pipelined control 3. Data Hazards 4. Forwarding 5. Branch Hazards 6. Performance 2chapter 6 Pipelining is Natural Car Wash Station (non-pipelined) Vacuum Wash Dry Brian Steve Brian Steve Brian Steve Brian Bob Steve Car Wash Station (pipelined) Vacuum Wash Dry Brian Steve Brian Bob Steve Brian Mike Bob Steve Brian Gorge Mike Bob Steve Vacuum, Wash, Dry each takes 5 minutes Nonpipelined Car Wash Station serving one customer per 15 minutes Pipelined Car Wash Station after the first customer (it takes 15 minutes), then every 5 minutes finishing service for a new customer 3chapter 6 What we learn from car wash station • Pipelining does not help latency of a single task, but it helps throughput of entire workload • Pipeline rate is limited by the slowest pipeline stage • Multiple tasks operating simultaneously using different resources • Potential speedup = Number of stages • Unbalanced lengths of pipe stages reduces speedup • Time to fill the pipe and time to drain the pipe -> reduce speedup • Stall the pipe for dependences 4chapter 6 Performance • Suppose we execute 100 instruction • single cycle implementation – 50 ns/cycle x 1 CPI x 100 inst. = 5000 ns • multiple cycle implementation – 10 ns/cycle x 4.6 CPI (instr. mix) x 100 inst = 4600 ns • ideal pipelined processor – 10 ns/cycle x (1 CPI x 100 inst + 4 cycle to fill up the pipe) = 1040 ns – here we assume that 5 stages in the pipeline – 5 stages : IF, ID, EX, MEM, WB Docsity.com Page 2 5chapter 6 Why pipeline ? Because the resources are there ! Why waste ! Start fetching and executing the next instruction before the current one has completed Remember the performance equation: CPU time = CPI * CC * IC Fetch (and execute) more than one instruction at a time Superscalar processing – stay tuned 6chapter 6 A Pipelined MIPS Processor • Start the next instruction before the current one has completed – improves throughput - total amount of work done in a given time – instruction latency (execution time, delay time, response time - time from the start of an instruction to its completion) is not reduced Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 IFetch Dec Exec Mem WBlw Cycle 7Cycle 6 Cycle 8 sw IFetch Dec Exec Mem WB R-type IFetch Dec Exec Mem WB » clock cycle (pipeline stage time) is limited by the slowest stage » for some instructions, some stages are wasted cycles 7chapter 6 Single Cycle, Multiple Cycle, vs. Pipeline Multiple Cycle Implementation: Clk Cycle 1 IFetch Dec Exec Mem WB Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9Cycle 10 IFetch Dec Exec Mem lw sw IFetch R-type lw IFetch Dec Exec Mem WB Pipeline Implementation: IFetch Dec Exec Mem WBsw IFetch Dec Exec Mem WBR-type Clk Single Cycle Implementation: lw sw Waste Cycle 1 Cycle 2 8chapter 6 MIPS Pipeline Datapath Modifications • What do we need to add/modify in our MIPS datapath? – State registers between each pipeline stage to isolate them Read Address Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 16 32 ALU Shift left 2 Add Data Memory Address Write Data Read DataIF et ch /D ec D ec /E xe c Ex ec /M em M em /W B IF:IFetch ID:Dec EX:Execute MEM: MemAccess WB: WriteBack System Clock Sign Extend Docsity.com Page 5 17chapter 6 Register Usage Can Cause Data Hazards ALUIM Reg DM Reg ALUIM Reg DM Reg ALUIM Reg DM Reg ALUIM Reg DM Reg ALUIM Reg DM Reg • Dependencies backward in time cause hazards add $1, sub $4,$1,$5 and $6,$1,$7 xor $4,$1,$5 or $8,$1,$9 • Read before write data hazard 18chapter 6 Loads Can Cause Data Hazards I n s t r. O r d e r lw $1,4($2) sub $4,$1,$5 and $6,$1,$7 xor $4,$1,$5 or $8,$1,$9 ALUIM Reg DM Reg ALUIM Reg DM Reg ALUIM Reg DM Reg ALUIM Reg DM Reg ALUIM Reg DM Reg • Dependencies backward in time cause hazards • Load-use data hazard 19chapter 6 stall stall One Way to “Fix” a Data Hazard I n s t r. O r d e r add $1, ALUIM Reg DM Reg sub $4,$1,$5 and $6,$1,$7 ALUIM Reg DM Reg ALUIM Reg DM Reg Can fix data hazard by waiting – stall – but impacts CPI 20chapter 6 Another Way to “Fix” a Data Hazard I n s t r. O r d e r add $1, ALUIM Reg DM Reg sub $4,$1,$5 and $6,$1,$7 ALUIM Reg DM Reg ALUIM Reg DM Reg Fix data hazards by forwarding results as soon as they are available to where they are needed xor $4,$1,$5 or $8,$1,$9 ALUIM Reg DM Reg ALUIM Reg DM Reg Docsity.com Page 6 21chapter 6 Another Way to “Fix” a Data Hazard ALUIM Reg DM Reg ALUIM Reg DM Reg ALUIM Reg DM Reg Fix data hazards by forwarding results as soon as they are available to where they are needed ALUIM Reg DM Reg ALUIM Reg DM Reg I n s t r. O r d e r add $1, sub $4,$1,$5 and $6,$1,$7 xor $4,$1,$5 or $8,$1,$9 22chapter 6 Forwarding with Load-use Data Hazards I n s t r. O r d e r lw $1,4($2) sub $4,$1,$5 and $6,$1,$7 xor $4,$1,$5 or $8,$1,$9 ALUIM Reg DM Reg ALUIM Reg DM Reg ALUIM Reg DM Reg ALUIM Reg DM Reg ALUIM Reg DM Reg 23chapter 6 Forwarding with Load-use Data Hazards ALUIM Reg DM Reg ALUIM Reg DM Reg ALUIM Reg DM Reg ALUIM Reg DM Reg ALUIM Reg DM Reg • Will still need one stall cycle even with forwarding I n s t r. O r d e r lw $1,4($2) sub $4,$1,$5 and $6,$1,$7 xor $4,$1,$5 or $8,$1,$9 24chapter 6 Branch Instructions Cause Control Hazards I n s t r. O r d e r lw Inst 4 Inst 3 beq ALUIM Reg DM Reg ALUIM Reg DM Reg ALUIM Reg DM Reg ALUIM Reg DM Reg • Dependencies backward in time cause hazards Docsity.com Page 7 25chapter 6 stall stall stall One Way to “Fix” a Control Hazard I n s t r. O r d e r beq ALUIM Reg DM Reg lw ALUIM Reg DM Reg ALUInst 3 IM Reg DM Fix branch hazard by waiting – stall – but affects CPI 26chapter 6 Corrected Datapath to Save RegWrite Addr • Need to preserve the destination register address in the pipeline state registers Read Address Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 16 32 ALU Shift left 2 Add Data Memory Address Write Data Read Data IF/ID Sign Extend ID/EX EX/MEM MEM/WB 27chapter 6 Corrected Datapath to Save RegWrite Addr • Need to preserve the destination register address in the pipeline state registers Read Address Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 16 32 ALU Shift left 2 Add Data Memory Address Write Data Read Data IF/ID Sign Extend ID/EX EX/MEM MEM/WB 28chapter 6 MIPS Pipeline Control Path Modifications • All control signals can be determined during Decode – and held in the state registers between pipeline stages Read Address Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 16 32 ALU Shift left 2 Add Data Memory Address Write Data Read Data IF/ID Sign Extend ID/EX EX/MEM MEM/WB Control Docsity.com