Pipelining - Intro to Computer Architecture - Lecture Slides, Slides of Computer Architecture and Organization

Download Pipelining - Intro to Computer Architecture - Lecture Slides and more Slides Computer Architecture and Organization in PDF only on Docsity! RISC Pipelining Docsity.com RISC Pipelining Classic five stage instruction Fetch – fetch instruction from memory Decode – determine what action is required Execute – execute instruction Memory – data cache access Writeback – write result to register Docsity.com RISC Pipelining  FI - fetch instruction  DI - decode instruction  EX - execute instruction  MEM – data cache access  WB - write back Instruction 1 2 3 4 5 6 7 8 9 1 FI DI EX MEM WB 2 FI DI EX MEM WB 3 FI DI EX MEM WB 4 FI DI EX MEM WB 5 FI DI EX MEM WB Docsity.com Pipeline Delay 1) move data from Mem1 to Reg1 2) move data from Reg2 to Reg1 3) move data from Reg1 to Mem2 FI DI EX MEM WB FI DI EX MEM WB FI DI EX MEM WB MOV Reg1, Mem1 MOV Reg1, Reg2 MOV Mem2, Reg1 (a) No data load delay in the pipeline Docsity.com Pipeline Delay FI DI EX MEM WB FI DI EX MEM WB MOV Reg1,Mem1 MOV Reg2,(Reg1) MOV Reg1,Mem1 MOV Reg2,(Reg1) FI DI EX MEM WB FI DI EX MEM WB Write data from Mem1 into Reg1 Must wait for data to be loaded into Reg1 Stall(bubble) 1) move data from Mem1 to Reg1 2) move data from Reg1 to Reg2 (b)Data dependency delay Docsity.com FI DI EX MEM WB FI DI EX MEM WB FI DI EX MEM WB FI DI EX MEM WB 101 ADD Reg3, Reg2, Reg1 102 NOP 103 BEQ Reg3 ,Reg4, 106 104 MOV Mem1, Reg3 105 ADD Reg4, Reg1, Reg2 106 MOV Mem1, Reg4 (c)Control dependency delay Reg3 = Reg4, jump to 106, no time wasted At this point Reg3 equal Reg2 + Reg1, and line 103 can compare Reg3 to Reg4 and decide jumping to 106 or not 101 add Reg2 to Reg1 and put in Reg3 102 no operation perform 103 if Reg3 = Reg4, jump to 106 else 104 104 move Reg3 to Mem1 105 add Reg2 to Reg1 and put in Reg4 106 move Reg4 to Mem1 Data dependency delay Guess branch will happen Docsity.com FI DI EX MEM WB FI DI EX MEM WB FI DI EX MEM WB FI DI EX FI DI FI DI FI FI 101 ADD Reg3, Reg2, Reg1 102 NOP 103 BEQ Reg3 ,Reg4, 106 104 MOV Mem1, Reg3 105 ADD Reg4, Reg1, Reg2 106 MOV Mem1, Reg4 107 MOV Reg2, Mem2 (c)Control dependency delay Reg3 not= Reg4, clear and fetch 104 next At this point Reg3 equal Reg2 + Reg1, and line 103 can compare Reg3 to Reg4 and decide jumping to 106 or not Data dependency delay Guess wrong can lead to wasted time Docsity.com Pure RISC Pipeline  Simple primitive instructions and addressing modes  Instructions execute in one clock cycle  Uniformed length instructions and fixed instruction format  Instructions interface with memory via fixed mechanisms (load/store)  Pipelining  Instruction set is orthogonal (little overlapping of instruction functionality)  Hardwired control  Complexity pushed to the compiler Docsity.com Pure RISC Pipeline Instruction 1 2 3 4 5 6 7 1 F E W 2 F E 3 F E 4 F E 5 F E W 100 move Mem1 to Reg1 101 add 1 to Reg1 102 Jump to 105 103 no operation 105 move Reg1 to Mem2 100 MOVE Reg1, Mem1 101 ADD 1, Reg1 102 JUMP 105 103 NOP 105 MOVE Mem2, Reg1 a) RISC Pipeline with inserted NOP A NOP is added so no special circuitry is needed to clear the pipeline F – fetch E – execute W – write back Docsity.com Pure RISC Pipeline Instruction 1 2 3 4 5 6 7 1 F E W 2 F E 3 F E 4 F E W 100 move Mem1 to Reg1 101 Jump to 105 102 add Reg1 to Reg2 105 move Reg1 to Mem2 100 MOVE Reg1, Mem1 101 JUMP 105 102 ADD 1, Reg1 105 MOVE Mem2, Reg1 a) Reversed instructions Delayed branch When a branch occur, delay the execution and fetch the next instruction first. ex) fetch 102 before executing JUMP to 105, this way 102 can execute at the same time 105 is fetch F – fetch E – execute W – write back Docsity.com Superpipeline A B C D E F G H I J K L A B C D E F G H I J K A B C D E F G H I J A B C D E F G H I A B C D E F G H A B C D E F G A B C D E F A B C D E A B C D A B C A B A A B C D E F G H In theory, more and shorter stages could allow more instructions to be process at the same time. But a branch could lead to wasted cycles. Branch executed and pipeline is clear Docsity.com