EELXE_7_Y2 Digital Circuits Exam - Autumn '08, Exams of Electrical Circuit Analysis

Download EELXE_7_Y2 Digital Circuits Exam - Autumn '08 and more Exams Electrical Circuit Analysis in PDF only on Docsity! Cork Institute of Technology Bachelor of Engineering in Electronic Engineering – Stage 2 (EELXE_7_Y2) Autumn 2008 DIGITAL CIRCUITS & SYSTEMS (Time: 3 Hours) Answer five questions All questions carry equal marks. Examiners: Mr. J. O’Driscoll Mr. M. O’Gorman Mr. D. Denieffe Dr. P. O’Sullivan 1. (a) State the factors that affect the switching speed of a bipolar junction transistor (BJT). [2 marks] With the aid of diagrams, indicate two ways in which the switching speed may be increased. [4 marks] (b) Compare TTL and CMOS logic circuits under the following headings: (i) size (ii) power consumption (iii) speed (iv) circuit complexity [8 marks] (c) Figure 1 shows the circuit of a TTL open-collector 2-input NAND gate. Briefly describe its operation. [4 marks] State where an open-collector logic gate might be used. [2 marks] Figure 1 2. (a) Briefly explain why a sample-and-hold circuit might be required when converting a analogue signal into a digital code. [4 marks] (b) Figure 2 shows the circuit diagram of a sample-and-hold circuit. Briefly describe its operation. [6 marks] Figure 2 (c) Draw circuit diagram of a 4-bit R-2R ladder digital-to-analogue converter. [6 marks] Describe its operation. [4 marks] 3. (a) Explain why a level translator is necessary to be able to connect the output of a TTL logic gate operating at VCC = +5 V to the input of a CMOS logic circuit operating at VDD = +10 V. [4 marks] (b) Figure 3 shows the circuit diagram of a discrete-component level translator connecting the output of a TTL gate to the input of a CMOS gate. Describe its operation. [8 marks] Figure 3 (c) The TTL output in Figure 3 is capable of driving 10 UL (unit loads). Calculate the number of standard TTL inputs can it drive in addition to the level translator. [8 marks]