PowerPC 750-Advance Computer Architecture-Lecture Slides, Slides of Advanced Computer Architecture

Download PowerPC 750-Advance Computer Architecture-Lecture Slides and more Slides Advanced Computer Architecture in PDF only on Docsity! Today’s Topics Case Studies  Power PC 750 Architecture  Power PC 970 Architecture  Intel Pentium – VI Architecture Summary docsity.com PowerPC 750 - General PowerPC 750 is an implementation of PowerPC microprocessor family of reduced instruction set computer (RISC) microprocessors 750 implements the 32-bit portion of the PowerPC architecture It provides 32-bit effective addresses for: – Integer data types of 8, 16, and 32 bits – Floating-point data types of 32 and 64 bits docsity.com PowerPC Instructions … Cont’d Floating-point instructions are: Floating-point arithmetic, multiply/add, rounding and conversion, compare, status and control instructions Load/store instructions are: Integer and Floating-point load and store; and atomic memory operations (lwarx and stwcx) instructions docsity.com PowerPC Instructions .. Cont’d Flow control instructions are: branching, condition register logical, trap, and other instructions that affect the instruction flow Processor control instructions are used for synchronizing memory accesses and management of caches, TLBs, and the segment registers Memory control instructions provide control of caches, TLBs, and SRs docsity.com PowerPC 750 Block Diagram docsity.com PowerPC 750: Instruction Flow (decode/dispatch) Fetch: Maximum 4 inst per cycle Instruction Queue Branch Processing Unit BPU) Dispatch Unit Max. 2 Inst/cycle; I Inst/unit Completion Queue Assignment Reservation Stations Store Queue Complete Completion Queue docsity.com PowerPC 750 – Instruction Fetch .. Cont’d However, the number of clock cycles necessary to request instructions from the memory system depends on where exactly is the: 1. branch target instruction cache 2. on-chip instruction L1 cache 3. L2 cache Having understood the instruction let us discuss how the PowerPC decodes and dispatch the instruction docsity.com PowerPC 750 – Decode/Dispatch Refer to the instruction flow diagram again and note that: – Instructions can be dispatched only from the two lowest instruction queue entries, IQ0 and IQ1 – A maximum of two instructions can be dispatched per clock cycle (although an additional branch instruction can be handled by the Branch Processing Unit-BPU – Only one instruction can be dispatched to each execution unit per clock cycle docsity.com PowerPC 750 – Execution Units Refer to the PowerPC 750 superscalar pipeline shown here and note that it contains two integer units (IUs), – IU1 can execute any integer instruction – IU2 can execute all integer instructions except multiply and divide Which share thirty-two GPRs for integer operands and a Single-entry reservation station for each docsity.com PowerPC 750 – Execution Units Furthermore, there exist – One three-stage floating point unit (FPU) that allows both single- and double-precision operations – Hardware support for demoralized numbers and Single-entry reservation station are provided – Thirty-two 64-bit FPRs for single- or double- precision operands docsity.com PowerPC 750 – Execution Units …..Cont’d Two-stage LSU (Load/Store Unit) contains – Two-entry reservation station – Single-cycle, pipelined cache access – Three-entry store queue Supports both big- and little-endian modes It’s dedicated adder performs (extended addition) EA calculations It performs alignment and precision conversion for floating-point data and sign extension for integer data docsity.com PowerPC 750 Rename Buffers 750 provides rename registers for holding instruction results before the completion commits them to the architected register Refer to the instruction flow diagram again and note that there are six GPR rename registers, six FPR rename registers, and one each for the CR, LR, and CTR When an instruction is dispatched to its execution unit, a rename register for the results of that instruction is assigned docsity.com PowerPC 750 Rename Buffers Dispatcher also provides a tag to the execution unit identifying the rename register that forwards the required data for an instruction When the source data reaches the rename register, execution can begin Results are transferred from the rename registers to the architected registers by the completion unit when an instruction is retired from completion queue Results of squashed instructions are flushed from the rename registers docsity.com PowerPC 750 Branch Prediction Unit Featuring both static and dynamic branch predictions, only one is used at any given time Static branch prediction – It is defined by the PowerPC architecture and involves encoding the branch instructions – The PowerPC architecture provides a field in branch instructions (the BO field) to allow software to hint whether a branch is likely to be taken docsity.com