Computer Architecture and Design Homework 9: Pipelined MIPS Processor and Cache Locality -, Assignments of Computer Architecture and Organization

Download Computer Architecture and Design Homework 9: Pipelined MIPS Processor and Cache Locality - and more Assignments Computer Architecture and Organization in PDF only on Docsity! ELEC 5200-002/6200-002 Computer Architecture and Design Fall 2006 Homework 9 Problems Assigned 12/1/06, due 12/6/06 Problem 1: Consider a five-stage pipelined MIPS processor that contains no hardware to handle hazards. Give an example of each type of hazard and explain how the software will handle it. Problem 2: Suppose we want to design a single finite state machine (FSM) to handle the entire control of a five-stage pipelined MIPS processor. In each clock cycle, this FSM directly generates control signals for all hardware units (ALU, RegWrite, MemRead, MemWrite, PC controls, all multiplexer controls, etc.) located anywhere in the pipeline. It should also handle hazards, forwarding, etc. What should be the input signals for this FSM? Note: You do not have to design the FSM. Problem 3: State the locality principle. Suppose we could determine that the size of a typical data locality is w words. How many blocks should a cache of m words (m is several times w) have? Given that the main memory contains M words and the program data may be located anywhere, what is the hit ratio for the first memory access the program makes? Will you expect the hit ratio to change on subsequent accesses?