Download Performance Analysis of Two-Stage AND-OR Logic Network in CMOS VLSI Design and more Assignments Computer Science in PDF only on Docsity! © Digital Integrated Circuits2nd Devices1 Fall 2005 – Assignment #7 Layout Design – Performance Characterization © 2003 Dr. James P. Davis Figures: Tanenbaum, 4th ed., © 1999, Prentice Hall Publishers, Weste et al., © 1993, Addison Wesley Publishers. Rabaey at al. © 2003, Prentice Hall Publishers CSCE 613 Introduction to CMOS VLSI Design © Digital Integrated Circuits2nd Devices2 CSCE 612 HW #7 – Problem Statement Circuit Design Topology We have a two-stage AND-OR logic network that is connected together, as shown, for XOR. Design Problem We want to carry out the following design & analysis tasks in a CMOS process: Carry out some performance analysis on the design by the following: – (a) given some specific values, solve for important parameters affecting performance—(1) parasitic capacitance for the devices and for the lines in the circuit, (2) delay, given the parameters provided by Rabaey et al. – (b) plot appropriate points on performance curves and select best tradeoff point for design elements under consideration.Source: Tanenbaum, 4 th ed. © 1999 Prentice Hall Publishing © Digital Integrated Circuits2nd Devices3 CSCE 612 HW#7 - Wiring Capacitance Data Process supports 1 layer Poly and 5 layers Metal. First 4 metal layers Use same H and tdi, But 5th layer has Hm5 = 2Hm and εdi5 > εdi . Use the Field values for C terms when placing wires over thick field oxide (SiO2) that isolates different transistors. Cpp values in upper row. Cfringe values in lower, shaded row. Table rows are capacitor’s “top plate. Table columns are its “bottom plate”. We’ll use Rabaey et al. Capacitance data for our problem (data is for a 0.25µ, rather than a 0.5µ, CMOS process, at VDD = 2.5v). © Digital Integrated Circuits2nd Devices4 CSCE 612 HW#7 - The Inverter Device & Circuit Static & Dynamic model High and low output levels are VDD and GND. “Ratio-less” nMOS and pMOS transistors (logic levels not dependent on transistor sizes) Finite RS resistance between the driving logic source (VDD or GND) and output. Low ZS output impedance, so less sensitive to noise or disturbances. High RL input resistance to the inverter (we’d see this in the 2nd inverter in the Buffer chain of our example). No direct path between VDD or GND. Capacitance Assume all device capacitances are lumped into a single capacitor, CL. We have composite CL: (1) gate-drain, (2) diffusion, (3) wiring, and (4) fan-out load gate capacitances. We’ll use the Inverter design as the basic cell for our layout problem involving line drivers for the load of a circuit block. V in V out CL V DD VDD VDD Vin Vout M1 M2 M3 M4Cdb2 Cdb1 Cgd12 Cw Cg4 Cg3 Vout2 Fanout Interconnect VoutVin CL Simplified Model
