Pulse-Width Modulated Converters: DC Transfer Functions and Associated AC Waveforms - Prof, Study notes of Electrical and Electronics Engineering

Download Pulse-Width Modulated Converters: DC Transfer Functions and Associated AC Waveforms - Prof and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! 1 LECTURE 5 PULSE-WIDTH MODULATED CONVERTERS AND ASSOCIATED AC WAVEFORMS A. REVIEW of unregulated ac mains to dc converters: vout control via duty cycle on time “D”; vout = vdc(in)*f(D) 1. DC TRANSFER FUNCTIONS f(D), where D = duty cycle on time, for buck, boost and buck-boost converters B. TYPICAL VOLTAGE AND CURRENT WAVEFORMS IN SIMPLE L-C OUTPUT FILTERS 1. INDUCTORS: vL (step) and iL (ramp) waveforms 2. CAPACITORS: ic (step) and vc (ramp) waveforms 3. Unsymmetric il and vc waveforms of equal integrated area 2 D D' L: Volt-sec balance C: Charge Balance D[Von, Ion] + D’[Voff, Ioff] ≡ 0 FOR STEADY STATE CONDITIONS 5 the high frequency switched mode has advantages as summarized below. Pulse-width modulated switch @ fs Duration "DT s" is the switch on time kHz<fs<MHz Vg DC Vout(dc) = f(Vg,D) ac The switched square wave output has two major components: Large signal DC and small signal ac. Vout = Vdc(average) + VAC(ripple) = Vgf(D) Large Small@fs 6 For an equal on/off square wave, D=D’=½, we can show by Fourier analysis that: Vdc(average) = V(peak)D. VAC = a Sin n n π 2    ∑ and an = 2V peakn ( ) π Fourier Components drop-off as 1/n. Fundamental component has 2V peak( ) π value. When we employ a series inductor in the output (not shown) VAC peak to peak at the output is usually reduced to ≤ 10% of the dc Vout provided the inductor is big enough.As the switch fsw varies from kHz up to MHz we can use smaller inductors to achieve the same level of ripple. fsw is usually limited to MHz & below because: •Fast solid state switches at high v and i are still limited to MHz values at high power levels •magnetic materials don’t work well above MHz. Magnetic core losses increase dramatically above 1 MHz due to hysterisis and eddy currents. SEE LATER LECTURES FOR DETAILS. To reduce the ripple component at fsw we add passive simple R-C or even L-C filters after the switch and before the load with L in series to limit kvl violations and C across the output to reduce ac variations. This double L-C action allows us to reduce the ac ripple on the dc output to designated levels. similar filters are put at the input to prevent switched waveforms from polluting the mains. There are now laws for allowable NOISE YOU CAN CONDUCT ONTO THE AC MAINS that originate in the switch-mode power supply. WE WILL ANALYZE BOTH CASES SEPERATELY LATER. In this lecture we focus only on output DC filters as a first case. 7 Switching Circuit and L, C Switch Network and Filtering DC source Vg Vout(dc) = Vgf(D) ac Vo(dc) may be less or more than Vg(dc) in general on D off D' Ts Switching D+D'=1 We actively control "D", the on time, via control circuits to vary Vout(dc) to desired level Switching Signal Waveform Vsw Control signal at fsw 10 IF IC IS A STEP DURING DTS THEN VC IS A RAMP DURING DTS I IC/C DTs Slope of ramp is ic/c with units of (v/sec) Note for both i and v to reach steady state after a full period of ts the following integral relationships must hold: L: C: v dt 0 i dt 0 L 0 T C 0 T s s ∫ ∫ = = For achieving steady-state during the D’Ts interval, we must return to DC levels that started DTs period. This means the net area under the vL and iC curves must cancel. For the L case this is termed “volt-sec balance” and for the C case it is termed “charge balance.” Note as dt decreases when fsw increases the balance is closer to zero in magnitude for fixed vL and iC values. 3. DC TRANSFER FUNCTIONS f(D) FOR BUCK, BOOST, AND BUCK-BOOST Below we again summarize vout/vin = f(d) relations for three basic converters that we will derive later. We will do this repeatedly to allow vout/vin = f(d) to be better understood when we are doing L(D), C(D) and L(D)-C(D) filtering design calculations. Note component choice depends on D values. We state again that the inductor or capacitor required to achieve a specified level of ripple on the output of a PWM converted will depend on the operating range of D. Design will have to account for worst case situations, as we will show in detail in Lecture 7 11 SIMPLE SWITCH MODE CONVERTERS D C fs D/D' BUCK The buck is limited in that Vout < Vin only D f(D) 0 0.2 0.6 1.0 1.0 VL=Vo or VDC-Vo •f(D)=D •Never get negative output •Vo(min) = 0 D C fs BOOST The boost is limited in that Vout > Vin only D f(D) 0 0.2 0.6 1.0 5 1 3 •f(D)=1/(1-D) •Never get zero output: Vo(min) ≠ 0 VL=VDC-Vo or Vo D C fs D/D' BUCK-BOOST The buck-boost is limited to negative voltages D 0.2 0.6 1.00 -1 -3 -5 f(D) •f(D)=-D/(1-D) •Inverting output w.r.t. Vg VL = Vo = -VDC for D = ½ 4. UNSYMMETRIC iL AND vC WAVEFORMS OF EQUAL INTEGRATED AREA IN THE ABOVE THREE CONVERTERS 12 D D' L: Volt-sec balance so iL ≠ ∞ C: Charge Balance so vc ≠ ∞ SINCE IN STEADY STATE: VDC AND Vout ARE BOTH MOSTLY DC BUT VDC ≠ Vout During switching pulsed dc steps are applied to the inductor VDC Vo Notice for above three circuits vL is across the inductor and is unique during the d cycle. It will be either of two possibilities: +VDC - Vout FOR BOTH THE BUCK AND BOOST OR -VDC ONLY FOR BUCK-BOOST AS ON SIDE OF THE INDUCTOR IS AT GROUND. In practice vdc and vout are primarily crudely rectified AC which looks like dc levels to a first approximation. THUS DURING DTs INTERVAL WE CAN FIND iL(t): i 1 L v dtL L= ∫ where VL = Vg - Vout during DTs (buck, boost) VL = -VDC during D’Ts (buck-boost) iL = (Vg-Vo)/L Upward iL ramp for buck and boost with fixed (Vg - Vo) during D cycle Note also the polarity of Vout for buck-boost can be negative during the D’Ts cycle, so we get down ramp.