PWM - Computer Systems - Exam, Exams of Computer Science

Download PWM - Computer Systems - Exam and more Exams Computer Science in PDF only on Docsity! Cork Institute of Technology Bachelor of Engineering (Honours) in Electronic Engineering - Stage 3 (NFQ – Level 8) Spring 2006 COMPUTER SYSTEMS (Time: 3 Hours) Answer any four questions [each 25 marks] Maximum available marks is 100. Use appropriate comments and indentation in program code. PIC and 68000 instruction sets attached. Examiners: Mr. P Cogan Prof. G. Hurley Dr S. Foley Q1. (a) Describe the operation of the PIC 16F74 microcontroller’s Timer2 module with the help of a diagram (include only the main components). [6 marks] (b) Describe the generation of PWM (Pulse Width Modulation) using the PIC 16F74 with particular reference to resolution, PWM frequency and software versus hardware waveform generation. [6 marks] (c) Write an assembly language program for a PIC 16F74 with a crystal frequency of 4MHz that generates a 1kHz PWM waveform with a mark space ratio of 1:4 (20% duty cycle). [13 marks] Q2. (a) The PIC microcontroller is said to use Harvard architecture. Briefly discuss what this means. [6 marks] (b) Demonstrate how the PIC 16C74 ADC can be used to sample an analogue voltage using an assembly language example. [8 marks] (c) Design a PIC based controller that measures temperature from two sensors and controls an alarm and a mains operated heater. The controller maintains the average temperature read by the sensors at a pre-programmed level using the heater. It sounds the alarm if the temperature drops below a lower threshold or rises above an upper threshold. An alarm mute button will de-activate the alarm for 10 minutes. Draw the circuit diagram for your controller on the attached sheet (showing the pinout for the PIC) and give the algorithm for how your software will operate. State any assumptions that you made about the requirements of the design. [11 marks] continued overleaf …. 2 Q3. (a) Give an example of both a RISC processor and a CISC processor. With reference to these processors discuss how their approach to CPU architecture differs and indicate the advantages/disadvantages of both architectures. [8 marks] (b) In evaluating a microprocessor you need to consider many hardware features. Describe the most important of these and give examples of how they are implemented in a processor of your choice. [8 marks] (c) Write a note on the work carried out by a cache memory controller in a typical computer system. In particular mention any problems that the cache memory controller may have to overcome and explain what is meant by ‘associativity’ and ‘replacement strategy’. [9 marks] Q4. (a) Discuss exception handling on the 68000 with particular reference to the following; (i) exception / interrupt vectors (ii) priority levels (iii) exception groupings (iv) the difference between exceptions and interrupts (v) the sequence of events when an exception is responded to. [7 marks] (b) While the 68000 provides a limited number of software exceptions, these can be used to control a large number of functions. Give an example of how exceptions can be used to implement three simple mathematical functions efficiently using a 68000 assembly language program. Memory addresses 8016 to BC16 store the vectors for the software exceptions available to your program. List any assumptions that you make. [11 marks] (c) Compare and contrast the EIA-232 and EIA-485 serial communication standards. Use a block diagram to illustrate how communication could be achieved between two 68000 microprocessors using one of these standards. [7 marks] continued overleaf …. PIC Register Bank 0 Value en ome | ony | ens | ara | eke | sts | see | eer | seo | ogmisaa| ailite, Banko icon [NOR [Adgrozoing tis luaion usce conte of FSA to acdhoes data neray (ota physical vege) Oth TresRo| Timer module's (epuster jozh Pou Progeam Couater's (PC) Least Significant Byte juone 2oae}coon sO0G) loon [svatus® | ie | apm | aro | fo | po | z | oe [ ¢ [sos sxx|oore anny fos [rsa indie data nevo\y add Poiror fence soem sa =] [PORTA Date ath nhs win: PORTA pina whan rend teas] ou ee PORTS sts Latch whoa weiter: SOAR pis whan fend Sos PORTE Dale Leich when writny: POATG ptm wen ined ooo woofs wun PONTO Data Latch when waiter’ PORTO pina when yeaa TT o_o JoAnn POLATHO AT - - —_| Wits Butfer tor the upper § bits cf the Progam Counter los nvcow | cle | PRE inte [ROG | TOF | NTF | RBIF [oooe vean[eccs soe och [Pat psnie™| ADIe® Tae | soar | copne | Twser | want [ecos oove[ seus voce cor [pre eee = = Peeve eh [WBA | Noting rage fo the Leaat Signticant By» ote 1E>4 TAN wogitor hae aa] Fh TMARYA Holding recisier tor the #osi Significant Byte of the 16-bit TVR} recister pesca ae] ion preen — [= [rieebar | Frowan [Frosoen] "SG [waaics [Tastow] co sore ish [rare Timer? mecuio’s siete jeoae seve| ian [re0oN —_ [routes] rouroea] Tours |rouvsa] Tunaon | oka [Teowrso| aoe 2009 rah [sore Syneivonave Sorat Port Receive Bute Transrit Regist once sonoma see vas [eeroon | woo | eseov | sere | cx] eseus | Sorus | Sarat | Soewe [sous soos[sa00 cone 1a [ocennL | capuweConpareiPvn” Regetert (SE) roma soc oars ava teh |COPRIK Capiure/Compare/PWit Registert (MSS) pexxx xxx fous wuLN| tz [ecprcon = =| cepsx | comiy | copss | copra | coors | cop iain. 000] Yan [ReeTA ‘span | axe | san | crey | — | FeRR | OBRA | RxeO “ee Tah [ARES _{USART Taner Daw regio eeu Tan __[ROAEG | USART Avevive Dat resistor 2o09 6 __[CCPAAL | CapiwciCompareP Wad Rogan? (158) fexae_ ean 1Gh__[CoPAAR | CopurorGemparo/> waa Ranier (SB) reas: axon fsa wou fon eepmcon | = [= | cepm | corey [ocram | coraus | cram [commie | 0 acee) 00 cara seh |AORES® | vO Resut register omnes |aown wa] TA [meas | aves: | acoso | onee | one | cnse [estore] | AGN fone wel Togend: x= Unknown, o = anchanged, q = value depends Gh Condition, » = unimplemented, read as ‘0. Shaded locations are unimplemented, read as 0. Note 1: The upper byte of the program counter Is net directly accessible. PCLATH it a holding segister for the PG<1 28> 2: The RP and APt bits are teserved: always maintain these bits clear Other (nch power-up) RESETS inchice extemat RE: |: These registers can be addressed {rom eitner bark, through MGLR ard Watchdog Timer Reset PIC Register Bank 1 Votuson: | vauunon iAddress| © Name =| Bit “| bro | ens | eka | oes | enz | sh1 | oxo [sgRisaa | tee, Bank oh [Nr Addisecing this lation uses centers of FER to adthass dala memory (rot a physical regivied) Lore aor | tone 9aea] ath jopTionpeG| Anu | iNFeDG | ‘Toos | Tose | Pea | Pez | pei | eso [sue aita|isit saz san [Paik PregramGeurters (PC) Lassi Signifeant Byla eae eoae|asne saad) lean [stares ine@ | ae [oreo | 7S | eB fz [oc [| c_ fooer sxex[eea quad eth [FSn® indineet deta memoly abdnese pointer ee lesn (TRIS —_ [= = PPenTA Data Direction Ragiatar Tal een [TAISe PORTE Data Direction nagator Prereereed fsx [tise POATC Date Direction register msi 3403 sok TRISDE PORTD Date Direction cegistor 2a son | TRISE? ter | CBr | (soy [rerMODE| — [FORTE Data Drecton bis R060 jenn [pcuarnima) fF = —__[virte Burra tr tho uppar 5 bts ef ne Program Geunior —_ |--—6 een [nrcon | oi | pee | Toe | IWe | ABE | Tor | Wir | ABI roce lech __|PiEt Pspic®| ape | row [ te | sere | copne | tuawe | Turse |eouw evar, veor cove] leon | PIE@ oe ~ = = — Tecra een [POON - - =~ = - |= POR BOA lee = [Urimplemonted g = = leon —__JUnimpomentod = = lean = |[Uninpismonted = = seh | PRE Tima Pevied eegleter Fag was | ana aga fean|SSPADO | Synchronous Serial Pon (/°C mode) Adgrass reqlstar foans coos] samo aves loin _ | SSPSTAT ~ [=] om Te Ts kw Toa Tae ve cova) 00 nee 6h <= __|Unimpiomanted = = Ey —__[Unimpiomancse = = oh —__[Unienplonanise = = seh |TASTA esno | tee | xen [| sync | — | enon | rawr | Txe0 [oes -oru|saee -ct4l een |SFBRG [aud late Generates register pe08 Veco] asus sve aah ee = = sen = lusimpiarnentes, ae = v— face = |nmpernented = = 20h —_|vrimmementea = = oh —__[Urimplemonted = = fm faocowit - | - | - | — [| — | Pore [rere [pores ---~ a0 Togond: x= unknown, u = unchanged, q = valoe depends on condillen, -~ unimplemenied, ead as 0° ‘Shaded tocations are unimplanented, read as'0'. Note +: The upper byta of the program counter is not directly accessible, PCLATH is a holding tegistar for the PO<t2:8>. 2 The IRP and AP4 bits are reseived; always maintain these bits clear, _ 3; Olher [oan power-up) MEETS Inchide external REGET through MCLA and Watchdog Timer Fleset. a: These registers can be addressed irom ether bank, 68000 Instruction Set Summary RSet - See Cork Instirute of Technolog