Question Bank Analog and Digital electronics(17CS32), Study notes of Digital Electronics

Download Question Bank Analog and Digital electronics(17CS32) and more Study notes Digital Electronics in PDF only on Docsity! Question Bank Analog and Digital electronics(17CS32) Module 1: Field Effect transistors 1. Explain the working of CMOS, with its power consumption properties? 2. Explain construction and principle of operation of JFET along with its drain and trans-conductance characteristics? 3. Explain construction and principle of operation of D-MOSFET along with its drain and trans- conductance characteristics? 4. Explain construction and principle of operation of E-MOSFET along with its drain and trans- conductance characteristics? 5. Draw the cross-sectional view of an N channel JFET and explain its principle of operation, Draw the Ig vs Vds graph for different values of Vgs and highlight the different regions of operation. 6. Write the differences between JFETs and MOSFETs. 7. Draw the circuit for voltage divider configuration for E-MOSFET. a. Also derive the expression for the operating point. 8. For the self-bias configuration of Fig.2. Determine: (a) IDQ and VGSQ. (b) VDS and VD. b. 9. What is differences b/w ideal and practical op-amp amplifier? 10. With a neat diagram explain op-amp Schmitt Trigger circuit? 11. Explain astablemultivibrator using 555 timer? 12. Explain mono multivibrator using 555 timer? 13. Explain Comparator? How do you convert sine wave to rectangular output, using Op-Amp? 14. Explain the CMRR, Slew rate, PSRR and gain-bandwidth performance parameter of a practical op- amp? 15. Define slew rate of Op–Amp. (ii) Determine the cutoff frequency of OP–amp whose unity gain bandwidth is 1 MHz and open loop gain is 2 x 10 5 . (iii) List the expression for the output of non– inverting amplifier and inverting op-amp amplifier 16. What is an peak detector & absolute value circuit? Explain the functional principal, with the circuit? 17. Draw the circuit diagram of a current to voltage converter using opamps. What type of feedback is used in the circuit? What decides the maximum value of feedback resistance to be used in the circuit? 18. Draw the basic circuit of three op-amp instrumentation amplifier and explain its operation? 19. What is the main advantage of using a comparator with hysteresis over a conventional comparator? Explain with transfer characteristics? 20. What is a window comparator? Draw a circuit diagram of a window comparator that produces a low output for the input signal inside the window and high output for input outside the window. 21. What are the requirements of a good Instrumentation Amplifier? 22. What is an absolute value circuit? Explain the functional principal, with the circuit? 23. Draw the circuit diagrams, which introduce a phase-shift of 0 to -180 and 0 180 to 0 degrees for a sine wave input signal. 24. Draw the circuit diagram of a voltage follower. What are its closed loop voltage gain and bandwidth? 25. Distinguish between bistable,monostable and astablemultivibrators. Module 2: The Basic Gates. 1. Explain the logic circuit and truth table of the Inverter, OR gat and AND F(A,B,C,D,E,F,G)=∑(20,28,38,39,52,60,102,103,127) 33.Give twosimplifiedirredundantexpressionfor F(w,x,y,z)=∑(0,4,5,7,8,9,13,15) 34.DeterminesetofPrimeimplicantsforfunction F(w,x,y,z)=∑(0,1,2,5,7,8,9,10,13,15) 35.Minimizethefollowingfunctionwithdon’tcareterms usingQ.M.method f(A,B,C,D)=m(5,7,11,12,27,29)+d(14,20,21,22,23) f(A,B,C,D)=∑m(1,4,6,9,14,17,22,27,28,)+d(12,15,20,30,31) 36.Determine the set of Prime-implicants for function F(w,x,y,z)=∑(0,1,2,5,7,8,9,10,13,15) 37.Using Quine-McClauskeyobtainthe setof Primeimplicants for functionF(a,b,c,d,e)=∑(4,12,13,14,16,19,22,24,25,26,29,30)+ ∑d(1,3,5,20,27) 38.ProvethefollowingBooleanidentities: 1. A(B’+C)=AB’+AC 2. A(A+B’C)=A 3. A’B’+AB’+AB=A+B’ 39.Findminimalsumandminimalproductofthefollowing Booleanfunction. f(W,X,Y,Z)=∑m(0,1,3,7,8,12)+dc(5,10,13,14) 40.UsingQuineMcCluskeymethod,determinetheprime applicantsofthefollowingfunction. f(W,X,Y,Z)=∑m(7,9,12,13,14,15)+dc(4,11) Module 2: Data Processing Circuits. 1.Why is a Multiplexer called a Universal logic circuit? 2.Configure16 to1MUXusing4to1 MUX 3. Implementthef(x,y,z)= ∑m(0,4,5,6)function using8to1 MUX 4. Implementthef(x,y,z)= ∑m(0,1,2,7)functionusing4to1 MUX 5. Implementhef(w,x,y,z)= ∑m(0,1,5,6,15,7,10,9)function using8to1MUX.Treat a,bandcastheselectlines. 6. Implementtheaboveusing4to1MUXwithaandbasselect lines. 7. Implementthe Booleanfunction f(a,b,c,d)=∑m(4,5,7,8,10,12,15)using4to2MUX and external gatesif,aandbareconnectedtoselectlinesa1and a2respectively,canddareconnectedtoselectlinesa1and a2respectively. 8. Implementthe followingusing3to8decoderwithNAND outputsoractivelowoutputs F1(a,b,c)= ∑m(1,3,5,6);F2(a,b,c)= ∑m(0,2,5,6) 9. Defineparitygeneratorandparitychecker. 10. Defineanexcess-3to8421codeconverterusinga4to16 decoderwithanenableinputusingNANDgates,so asto minimizethegateinputs. 11.UsingdecoderimplementthefollowingLogicfunctions. a.ActiveHighdecoderwithORgate, b.ActiveLow decoder withNAND gate, c.ActiveHighdecoderwithNOR gate, d.ActiveLowdecoderwithANDgate. 12.Design2-4decoderwithenableinputE. 13.Design3-8decoder. 14.Design4-16decoder. 15.Mentiontheapplicationofdecoder. 16.Howmanyoutputsamagnitudecomparatorgenerates? 17.Showhowtwo1to16demultiplexercanbeconnectedtoget 1to32demultiplexer. 18.Designa32to1multiplexerusingtwo16to1multiplexersand one2to1multiplexer. 19.GivesevensegmentdecoderusingPLA. 20.Showthatusinga3-to-8decoderandmulti-inputOR gate, thefollowingexpressions canberealized. F1(A,B,C)=∑m(0,4,6);F2(A,B,C)=∑m(0,5); F3(A,B,C)=∑m(1,2,3,7) 21.DesignDecimaltoBCDencoder. 22.WhatarethedifferenttypesofPLDsandimplementthe7- segmentdecoder. 23.MentiondifferenttypesofROMSand explaineachoneofthem. 24.Whatarethedifferentmodelsfor writinga modulebody in Verilog HDL.Give anexampleforanyonemodel. 25.Realizethe Boolean expression f(w,x,y,z)=∑m(4,6,7,8,10,12,15)using4:1linemuxand externalgates. Module 4: Flip-Flops 1. Mentionthedifferencebetweencombinational&sequential circuitswithblockdiagram. 2. Mentionthedifferencebetweenasynchronous&synchronous circuitswithexample. 3. DifferencesbetweenLatch&Flipflopgiveexample. 4. Defineclockedsequentialcircuit. 5. DifferencebetweenCharacteristic&Excitationtable. 6. Explaintheoperationofdifferenttypesofflipflop. 7. WhatisRace aroundcondition.Explain. 8. ExplaintheoperationofJKflip-flop.Withlogicdiagram, characteristictable. 9. DiscusshowunstableconditionS=R=1isavoidedinstorage latchofthefollowing: a)Dlatchb)JKflipflop c)Tflipflop 10.ExplainclockedRSflipflopwithlogicdiagram. 11.ShowthatclockedDflip-flopcanbereducedbyonegate. 12.ExplainhowD&Tflipflopworkswithlogicdiagram. 15.Find the binary weight of each bit in a 4-bit system. 16.Whataretheoutputvoltagescausedbyeachbitina5-bit ladderiftheinputlevelsare0=0vand1=+10v 17.Howmanybitsarerequiredinabinaryladdertoachieve aresolutionof1mVif fullscaleis+5V 18.Findthe followingfor a 12-BitcountertypeA/D converterusing1-MHzclock: a.Maximumconversiontime,b.Averageconversiontime c.Maximumconversionrate. 19.Whatistheconversiontimeofa12-bitsection-counter- typeA/DConverterusing1–MHz clock?Thecounteris dividedintothreeparts. 20.Whatistheresolutionofa9-bitD/Aconverterwhichuses 9laddernetworks?Whatis theresolutionexpressedasa percent?Ifthefull-scaleoutputvoltageofthisconverter is +5v,whatistheresolutioninvolts? 21. Explainwiththeblockdiagramofsuccessiveapproximation ADC. 22. Whatisabinaryladder?Explainthebinaryladderwith digitalinputof1000. 23.ExplainaccuracyandresolutionforADC. 24.Explaina2-bitsimultaneousA/Dconverter.Drawtheblock diagramof thesame. 25.ExplaincontinuousA/Dconverterwithanexample.