Quiz on The Whole Memory Hierarchy - Systems and Networks | CS 2200, Quizzes of Computer Science

Download Quiz on The Whole Memory Hierarchy - Systems and Networks | CS 2200 and more Quizzes Computer Science in PDF only on Docsity! The Whole Memory Hierarchy: Briefly describe how a LW instruction would put data into a register. (Assume a “best case/no penalty” scenario). Hint: think about the memory hierarchy that we’ve talked about for the past few weeks and what kinds of addresses there can be…). Suggestion: make a bulleted list of steps: Answer: 1. CPU supplied a virtual address 2. The virtual address tag is found in the TLB 3. The portion of a physical address associated with a given virtual address is concatenated with offset of the virtual address to form a complete virtual address 4. The physical address is used to index the cache: a. Offset picks a specific word from a cache block entry b. Index picks a specific cache block entry c. Left over bits form the tag and are compared against the tag associated with a given cache block entry 5. (In the “best case”, the tag of a physical address and tag of a cache block match; also, the valid bit of a cache entry is set…) 6. The word is/has been identified and can be moved to the register Now, what can go wrong with this “best case” scenario and when does it happens. You should identify 3 things… Answer: 1. The virtual address tag is NOT found in the TLB a. We should first try to find the upper part of our physical address in our page table i. (The page table is stored in main memory…) ii. If we find our entry in the page table, we now have the location of our physical page frame b. If found, we update our TLB and only have to pay a TLB miss stall penalty – which is essentially a main memory access…) 2. The physical page frame number is not found in the page table… a. There are two ways that this could happen: i. The entry is not there (i.e. it’s simply not loaded…) ii. The valid bit is not set b. In this case, we actually have to get our data from disk i. We pay a penalty of a TLB miss stall as well as the penalty of going off to disk (this is the absolute worst case scenario…) 3. We have a cache miss… a. There are 2 ways that this can happen: i. The entry is simply not in the cache (i.e. we map to a particular cache entry and there is no tag match) ii. The valid bit is not set (meaning that randomly the tags match, but a program never put data in the cache…) b. What happens? We’ll have some sort of a cache miss stall… i. There could be a level 1 cache miss, but a level 2 cache hit ii. There could be a level 1 and level 2 cache miss – requiring a main memory access Fundamental Cache Math: You have been asked to design a cache with the following properties:  Data words are 4 bits each 2048 blocks/8 = 256 sets in the cache  A cache block will contain 1024 bits of data (therefore index is 8 bits long…)  The cache is 8-way set associative  The physical address is 50 bits long Block offset = 1024/4 = 64 = 28  There are 2048 blocks in the cache (therefore block offset is 6 bits long…)  Addresses are to the word Page 1 of 5 Tag = 50 – 8 – 6 = 14 bits… Pictured below is the general structure of a cache. There are 8 fields (labeled a, b, c, d, e, f, g, and h). In the space below you’ll need to indicate the proper name or number of bits for a particular portion of this cache configuration. Whether a name or number should be entered will be specified: f. g. <a. > <b.> <c.> <d.> <e.> ... … Mux=?=? Data in Data out CPU Address Write Buffer Lower level memory h. ……… … ……… … i. a. (number) 34 g. (name) index b. (number) 8 h. (name) block offset c. (number) 8 i. What 3 things must be compared at i./? to determine if the cache entry is d. (number) 34 usable or not? tag of address, tag in cache, valid bit e. (number) 1024 (bits) f. (name) tag j. What is the total size of the cache? 2048 * 1024 bits * 1byte/8bits = 256KB A Virtual Memory Question:  Given 8KB pages, 6 bytes / page table entry, and a 33 bit virtual address, how big is the page table?  To see if you understand how and where they fit into the memory hierarchy – and to get a feel for their relative sizes – draw a sketch of the page table, a page, and main memory. Answer:  Offset = 8 KB = 13 bits = 213 = 8192 (8K) Page 2 of 5