Repeated - Introduction to Microelectronic Circuits - Solved Exam, Exams of Microelectronic Circuits

Download Repeated - Introduction to Microelectronic Circuits - Solved Exam and more Exams Microelectronic Circuits in PDF only on Docsity! UNIVERSITY OF CALIFORNIA Coliége of Hagineecing ‘Department of Elecitical Eugincering ‘ad Computer Sciciices Professor Oldham ee mB 20000 EECS 40 — FINAL EXAM Seg ee Saturday, 16 December-2000, 8:00 -' 11:00 a.m. / : Name: : oe ’ Student ID: Last, First - : , : Signature: Sok VP ions TA: OBen-- Q Warren: O Naratip - Guidelines: : 1.. Closed book and notes except 1 page of formulas. 2.. You may use a calculator. 3. Do not unstaple the exam. . 4. Show all your work and reasoning on the exam in order to receive full or partial credit. 5. Caution: NO CREDIT will be given for answers not in answer boxes; : 6. This exam contains 8 problems and corresponding worksheets plus the:cover page. ‘Points Your, Problem Possible Store 1 12 2 12 3 12 4: 12. 5 14 6 12 7 12. 8 14 Total 100 : £5 = 8.85 <10-"4 Flenl Problem 1 (12 points) (a) : oy 2K ee 2K 2K . + sv . 10pF == Cov The switch closes at ¢ =-0. (a.1) What is V, at t= 0*? al V,@= 01) = 10MM: (a:2) What is i.. at t =.0+? + : ) 2 a0 AT goons On wlio? — | 2K i, 0°) = -BmQ = lee -BmA 2k (a.3) What is i, at t= 0*? : f a3 i, (tao) = lo-~ Valter OY . p-lo "i204 = O mA ak 2K =O ay, (a.4) What is a attr = 0+? Cady 2 tk 9 dV. = “S.40.-5mA “ws = 5108 (L de ¥ bs at boot é oxo 6 dt | ge : (3) (a.5) Draw very neatly the graph of V, versus time on the axes provided opposite. (You MUST put scales on the axes to receive full-credit.) (a.6) Write an equation for V(t). 02 545 exp thor®) | Probl ‘ont. (bo. Dit v,t0) is initially zero and suddenly j jumps to Yop 3 can. n'you ‘write: an expression for the stage delay tp tL? as Le., the-time it takes F, ‘to’ go, from Vp: to Vinp/2 in terns of device parameters Ry Rp» ep Te Cons Cap )?-Note: Ignore. wiring capacitance and do not evaluate numerically..." : Ss Pp wetness! BE Tur = Ov6TR-C where a B Ray and: ‘es “3Cop: teow #2 Lop (foimulas only) 2, #2 é Ge. (b.2) In the.same-circuit above Y; ‘in(t) is'a square wave going from 0 to Yop 10.0, ate: We are interested i in, worst” case delay. Which transient is slower: tp) OF T, DLN? Answer the question by checking one of the three boxes. : “ ba" : (2) tore> tour. : ToL <THaL EJ "DLE Star (b.3) Why? (Explain answer to b.2.) " 3Rn > Rp  it Analysi oint Find Vj in terms of V,2j,R,; Ry. 3 Mal 4 Ye Ry Ra Vs =a LW RRR Check: *Yes” or “No” for each item inthe following. - table: © . . wee . Yes No ¢ My, depends on. Vy. ? x . “Ry x " Ry? x “ Ry? ee " Ry 2. on " Rot | iw {a marks) : (3) Qe + Find V,. 6V. : & : “Sw @roma > sinew diode te oa fet XS . . Le ree r perfect rectifier. ne voltage rectifier. , oy = >= dvop Cay: exist across U. Vi=. 6 (Wy * V, toe (2 marks) =~ (d) - i + Find V,,. 3V 2K mA Vv y + Orma-Y- ‘on: the Apply KVL on. vine ¥y = “Sv wy outermost, wep’. Find. V; in terms of Vin eRyy Rae Vag + SVQ. = 6¥4 BVg 8 : oe u * u Bat 1é& blem 4 —~ Op-Amp Circuits (12 point: Note: Assume that all op-amps are ideal except that they have rails of +5V.. IK vl = Nout Ving = Ze) v= GYAN) = av | (Volt Aividst ) {K+ 2K. Ve Wort lv é Fill out the table: ) oe ee —— ‘ Aralo hic [Taw uh, Va Va Ve MW) Vou WY) ‘ Vout 4 -Y, ti -fVa Vv, v k)y* vit re * YB + Xe JH) 1 wl ~ a Ng a ® 4 Vout tov e Mt Vary Ve (c) Find and sketch the Thévénin Equivalent of this op-amp circuit (from terminals A-B). 10K vi i0K 7 A VA Mog = v‘* iv Vv. Ok Pl P80 ron 0k ok @iv B 7 ve Be— Tye how iV Ry * lol (d). Find and sketch the Norton Equivalent of this op-amp circuit (from terminals A-B). SORE Su 7 0f 16 Pp 6 ints : Find the Thévénin equivalent cifcuits of the following. (You must draw: solution in-box provided.) = 2.5 is Tow Ah i ER, \ne “eee au wad &* “Rive eae 3K 1K: ire Soper © ae > a 2h a int: Use Siperposition V2 BV: : rus We : % i) Ae Spa o 3 ) pm alc vO > Fm “ Nive ae Wh cy Bo &. igre DVI Ra rguidke Ae— Re ov + ° Vee’ Use Tee WN test Rone “Le Tes In gsnteRe TT Re Aap ee Rm Te [1+ GRE = Re TB e) A, bed : od 4® Ry / . : Ra BS -TwRa Be—_ : Rrus RA oop os 7 Vw = 7 Ta Re da) Be— Ht 2 Re + (BARE . blem 7 rand-F 12 (a). The'switch closes at:t = 0.Then we wait-a Tong time. Find.the energy: Sa ESO 2K ] -L. 1pF (a.1) delivered by: the: power supply. ~ 10V (initially uncharged) : (a.2) dissipated i inthe resistor, (a.3) delivered to the capacitor. ave ound al 20-4 © units WI” (Answers must appear in answer boxes and. — : mist have units.) Leyte 0.08ms Lev = 005m a2.0.05.- units mT" wey : : 4 ev 2 0.05MI) a3" O08 units mS V, (2) is a square wave. switching every Ipsec. Itis going from +2V to-OV, back to +2V,.etc. (Period is 2uséc.) (b.1) What is the average P power delivered. by V,‘inmW? . Pins oA C2 2 mw bt pS do mw 2 2 CR +R) 2 OR . . (be com isthe ay average power dissipated in each. of the resis- 7 ° Py = 25 mW i 5? . : Bi R., Ry Re Rove same veltoge drape Pay = OS mW... ¢ 2 £04) : Pa; = 2.5. mW Perey = 4 40". 05 enw 2 Be : au Pa, = 2S mW Op arp aut pdt wobtage | 1S Square yreure, poe ERA ote: 2¥: 1 Pag = 0-002 mw Peg os 2 Cv oe 4 (1p)<2)" Ue . (b.3) What is the average power “net di a the capacitor? 2 2M@N[" 5 itr deca vet dissipate ba PO _mw omy, Camnoge) power. (b.4) Where. does: the energy dissipated in R23 fina come from? 2 At é 9 Prob) = Drain I-V (14 poi The drain I-V characteristics of one of the Berkeley world record-setting PMOS "FinFet" devices are given opposite. The device has a channel length of only 40 nm. This device has.a width of ipm and a gate oxide thick- ness of 2 nm. If we assume a (~)0.25V threshold, we note that in saturation it seems to obey our model equation: In = Ips(1+AlV pg |) where Ww - . Ing = ky I (Vgs~- Vp. (Note: Vas. Vins: Ip» Ips, Vr are all negative for PMOS.) We intend to use this device in a circuit with logic values corresponding to ~ 0V and ~ 1V, using, of course, a 1V power supply. (a) Device parameters: a.1) What is ky for this device (20% accuracy)? a.2) What is 4 (20% accuracy)? (b) Basic inverter: In the absence of an NMOS device we Yop can still make an inverter with a resistor and power sup- ply. Suppose we hook up the device-as follows: (b.1) For this inverter you are to estimate the output Ya — voltage at several values of input voltage; in par- ticular, fill out the table opposite. An accuracy of .05 V is adequate. In order to estimate the performance of this CMOS inverter, we consider a chain of identi- cal inverters. Stage 1 and 2 are shown at the Vin —d vy right. Suppose the input to stage 1 is low (~0V): 3K Stage 1 (b.2).The Berkeley designers believe that for this inverter a sensible [p2 logic “0” range might be 0 < V<0.25V. What might be a'sensible |) 0.75 < Ve | voltage range to define as “1”? ky = 16 units AAV A= 0.\ units | etc. Stage 2 (b.3) Now we want to consider the transient. If we ignore inter-' [3 connect and drain capacitances, what is the capacitance loading the output node of stage 1? Give both a formula in terms of the circuit capacitances and evaluate for the numerical value. C= Se wel (formula) C= 64 9 UF) (numerical value) (b.4) The input to stage 1.is suddenly switched from OV to iV, We expect the output of stage 1 to go from high to low. You have already computed the capacitance in question (b.3); now compute the resis- tance governing this transient. And compute the time for the output to reach 0.25V (formula and value). PLEASE NOTE ANSWER BOXES OPPOSITE. 15 of 16