Moore's Law and the Future of Technology: Exponential Growth Trends and Challenges, Slides of Introduction to Computers

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Riding the Technology Curve Dec. 1, 1998 Topics n Moore’s Law n Are exponential problems intractable? n Impact on real-world problems n The verification challenge 15-213 – 2 – Impact of Technology It’s the Technology, Stupid! n Computer science has ridden the wave Things Aren’t Over Yet n Technology will continue to progress along current growth curves n For at least 10 more years n Difficult technical challenges in doing so Even Technologists Can’t Beat Laws of Physics – 5 – Impact of Moore’s Law Moore’s Law n Performance factors of systems built with integrated circuit technology follow exponential curve n E.g., computer speed / memory capacities double every 1.5 years Implications n Computers 10 years from now will run 100 X faster n Problems that appear intractable today will be straightforward n Must not limit future planning with today’s technology Example Application Domains n Speech recognition l Will be routinely done with handheld devices n Breaking secret codes l Need to use large enough encryption keys – 6 – Solving Hard Problems Conventional Wisdom n Exponential problems are intractable Operation n Assume problem of size n requires 2n steps n Each step takes k years on a Y2K computer Y2K Computer Performance n Start computation Jan. 1, 2000 n Keep running same machine until problem solved n Would take k 2n years – 7 – Solving with a Y2K Computer Y2K Computer 1.E-05 1.E-03 1.E-01 1.E+01 1.E+03 1.E+05 1.E+07 1.E+09 1.E+11 1.E+13 1.E+15 1.E+17 1.E+19 1.E+21 1.E+23 1.E+25 1.E+27 1.E+29 1.E+31 10 20 30 40 50 60 70 80 90 100 Problem Size (n) C P U Y ea rs second minute hour day week year Time per Operation – 10 – Solving with a Moore’s Law Computer Moore's Law Computer 0 20 40 60 80 100 120 140 160 10 20 30 40 50 60 70 80 90 100 Problem size (n) C P U Y ea rs second minute hour day week year Time per Operation – 11 – Effect of Step Complexity Observe n Step complexity k adds only additive factor of 2.16 ln k to running time Example n For n = 100 k y 1 second 111 1 minute 120 1 hour 129 1 day 136 1 week 140 1 year 148 Explanation n Final years of computation will be on exponentially faster machines – 12 – Implications of Moore’s Law P=NP (Effectively) n Problems of exponential complexity can be solved in linear time Caveat n Cannot hold forever Fundamental Limit n Argument due to Ed Fredkin n Claim that ultimate limit to growth in memory capacity is cubic n Cannot build storage device with less than one electron n Assume consume all available material to build memories l Would soon exhaust planetary resources l Cannot travel into outer space faster than speed of light n Total amount of material available at time t is Ω(t3) n This limit will be hit in ~400 years – 15 – Motivation for Formal Verification Intel’s Challenge, (ca. 1992) n Design a high performance, state of the art microprocessor to succeed the 486 n Maintain compatibility to 20-year old x86 product line n Provide new levels of performance on floating point Floating Point Divider n Use radix-4, SRT algorithm developed in 1960’s n First time ever used by Intel Validation n Run lots of simulation tests n Make sure it runs set of Windows applications Manufacturing Environment n Will produce millions of chips n Cannot make any changes after manufacture – 16 – The Pentium Fiasco Events n Prof. Thomas Nicely, Lynchburg College, VA l Looking at properties of “twin primes” l Incorrect reciprocals for 824633702441 and 824633702443 » ~ Single precision accuracy (4 X 10–9) l Contacted others on Oct. 30, ‘94 n Spreading of Information on Internet news group comp.sys.intel l Terje Mathisen of Norway posts Nicely’s findings on Nov. 3 l Andreas Kaiser of Germany finds 23 bad reciprocals, Nov. 10 n Tim Coe, Vitesse Semiconductor, Nov. 16 l Created (good enough) software model of flawed divide algorithm l Discovered (nonreciprocal) cases with errror up to 6 X 10–5 l Later showed 1738 mantissa pairs with less than single precision accuracy » out of 7.4 X 1013 single precision mantissa pairs – 17 – Resolution Free Replacement Policy, Dec. 20 n No need to argue need n Complex logistics l Many different versions l Actual replacement easy Financial Impact n Intel charged $475 million to it’s 4Q94 earnings n Still was 2nd most profitable year ever n Few companies could survive such an expensive mistake n In the end, generated lots of valuable PR for Intel – 20 – Temporal Logic Model Checking Verifying Reactive Systems n Construct state machine representation of reactive system l Nondeterminism expresses range of possible behaviors l “Product” of component state machines n Express desired behavior as formula in temporal logic n Determine whether or not property holds Traffic Light Controller Design Traffic Light Controller Design “It is never possible to have a green light for both N-S and E-W.” Model Checker True False + Counterexample – 21 – Word-Level Abstractions n View bundle of wires as encoding numeric value n Represent as function l Over Boolean variables l Yielding numeric value • • • x0 x1 xn–1 ENC x X Bit-Level Signals Signal Bundle Word Signal Example Encoding Function ◆ Unsigned binary X = x0 + 2 x1 + 4 x2 + … + 2n–1 xn–1 Encoding Function – 22 – Word-Level Verification nLai [USC], Vrudhula [Arizona] Given nBit-level circuit representation nEncodings of inputs and outputs nWord-level specification Compare nCorrespondence between two representations nUnder I/O encoding Observation nCrossing abstraction boundary ENC x X ENC Spec: P = X⋅Y y Y P x Multiplier Circuit y ENC Pp – 25 – Using Word-Level Verification Word-Level Model Checking n Xudong Zhao, CMU PhD ‘97 Idea n Introduce word-level specifications into model checker’s specification language n Implement with combination of BDDs and BMDs Applying to Intel’s Circuits n Verified that each iteration of SRT divider is correct n Major breakthrough for Intel n Still cannot do “end-to-end” verification of divider – 26 – Recent Result on Arithmetic Circuits n Yirng-An Chen, PhD ‘98 Verifying Floating Point Adders n Able to automatic verify complete behavior, including rounding n That it realizes IEEE FP standard n Completely “hands-off” l No guidance from user on how circuit really works exp significandsA exp significandsB Floating Point Adder exp significands Rounded Sum – 27 – Formal Verification Tasks Digital Circuits n Arithmetic circuits l “Does this circuit compute the specified mathematical operation?” n Pipelined processors l “Does this circuit implement the specified instruction set?” Reactive Systems n Cache protocols l “Is it possible for 2 processors to have write access to a single block?” n Controllers l “If a car approaches the traffic light, will it eventually turn green?” Software Systems n Operating Systems l “Is it possible for the scheduler to exclude a process indefinitely?”