Resistors - Microelectronic Devices and Circuits - Exam, Exams of Microelectronic Circuits

Download Resistors - Microelectronic Devices and Circuits - Exam and more Exams Microelectronic Circuits in PDF only on Docsity! 1 University of California at Berkeley College of Engineering Dept. of Electrical Engineering and Computer Sciences EE 105 Midterm I Spring 2002 Prof. Roger T. Howe March 6, 2002 Your Name: ______________________________ Student ID Number: ________________________ Guidelines Closed book and notes; one 8.5” x 11” page (both sides) of your own notes is allowed. You may use a calculator. Do not unstaple the exam. Show all your work and reasoning on the exam in order to receive full or partial credit. Score Problem Points Possible Score 1 17 2 17 3 16 Total 50 2 1. IC resistors [17 points] Oxide Mask (dark field) Metal Mask (clear field) 0.5 µm Contact Mask (dark field) 2 1 2 3 4 5 6 x, [µm] 0 1 Polysilicon Mask (clear field) 1.5 µm X 1.5 µm A’ A 0.5 µm 2 µm 3 µm 4 µm Process Sequence: 1. Starting material: p-type silicon wafer with a doping concentration of 1 x 1017 cm-3 2. Deposit a 250 nm-thick SiO 2 layer 3. Deposit a 250 nm-thick layer of n-type polysilicon and pattern using the Polysilicon Mask (clear field). 4. Pattern the oxide using the Oxide Mask (dark field). 5. Implant phosphorus with dose Qd = 5 x 1012 cm-2 and anneal to form a 250 nm-thick phosphorus-doped region. 6. Deposit a 250 nm-thick SiO 2 layer and pattern using the Contact Mask (dark field). 7. Deposit 250 nm of aluminum and pattern using the Metal Mask (clear field). 5 2. MOS charge-storage element [17 pts.] n+ p G B1 B2 B1 B2 A A’ A A’ 8 µm 8 µm 12 µm 1 2 The MOS structure shown in cross section and top view above has a metal gate and two bottom electrodes, B1 (p substrate) and B2 (n+ layer). The bottom electrodes are contacted by a metal line and shorted together, as indicated on the top view. The oxide thickness is tox = 11.5 nm for the MOS structure and the oxide permittivity is εox = 3. 45 x 10-13 F/cm. In region 1, the p-type substrate is the bottom electrode and the MOS parameters are: VFB = -1.2 V, VTn = 0.8 V In region 2, the n+ layer is the bottom electrode and the MOS parameters are: VFB = -0.2 V, VTp = -3 V 6 The charge storage curves for the two regions are provided on the graphs below of gate charge per unit area versus the gate-bottom electrode potential, vGB. Since B1 = B2, we use “B” to represent the potential of the bottom electrode for each region. vGB [V] qG [fC/µm2] -1 1 2 3 -2 -3 -4 4 0 5 10 -5 -10 Region 1 Region 2 (a) [4 pts.] For vGB = 1 V, find the total charge on the gate (units: femtoCoulombs = 10-15 C). (b) [4 pts.] For vGB = -1.5 V, identify the substrate charge in regions 1 and 2 by circling the correct description(s). Note: the correct answer may have more than one item circled. Region 1. ionized acceptors accumulated holes inversion-layer electrons Region 2. ionized donors accumulated electrons inversion-layer holes qG,Total = fC 7 (c) [4 pts.] For vGB = +1.5 V, identify the substrate charge in regions 1 and 2 by circling the correct description(s). Note: the correct answer may have more than one item circled. Region 1. ionized acceptors accumulated holes inversion-layer electrons Region 2. ionized donors accumulated electrons inversion-layer holes (d) [3 pts.] If we apply a voltage vGB (t) = 0 V + vgbcos(ωt), where vgb=5 mV and ω = 2π(106) rad/s, find the current igb(t) into the gate terminal in nA from the charge-storage curves. (e) [2 pts.] The maximum capacitance of the MOS structure is Cmax. If the DC component of vGB is 1.5 V, what is the maximum amplitude of its small-signal component vgb(t) for which the current remains exactly proportional to Cmax.