VLSI Design System: Lecture 7 - Static Dynamic CMOS Inverter - Prof. Aurangzeb Khan, Study notes of Electrical and Electronics Engineering

Download VLSI Design System: Lecture 7 - Static Dynamic CMOS Inverter - Prof. Aurangzeb Khan and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! EE534 VLSI Design System Summer 2004 Lecture 7: Static Dynamic CMOS inverter (CHAPTER 6) Review: CMOS inverter design consideration The CMOS inverter usually design to have, (i) VTN =|VTP| (ii) K´n(W/L)=K´p(W/L) But K´n> K´p (because µn>µp) How equation (ii) can be satisfied? This can be achieved if width of the PMOS is made two or three times than that of the NMOS device. This is very important in order to provide a symmetrical VTC, results in wide noise margin. Review: Noise margin calculations Vout = VDS D ra in c ur re nt I D S Vin=2V VCC Vin=1V Vin=3V Vin=4V NML=VIL-VOL (noise margin for low input) NMH=VOH-VIH (noise margin for high input) Review: CMOS inverter: VIL and VIH for Ideal VTH (Symmetrical, Kn=Kp) Assuming VT0,n=-VT0,p, and kR = 1, ( )0238 1 TCCIL VVV += ( )0258 1 TCCIH VVV −= (symmetrical inverter) R nTRCCpTout IL k VkVVV V + +−+ = 1 2 ,0,0 ( ) R nToutRpTCC IH k VVkVV V + +++ = 1 2 ,0,0 (asymmetrical inverter) NML=VIL-VOL (noise margin for low input) NMH=VOH-VIH (noise margin for high input) Review: CMOS inverter: VTH KCL: Solve for VTH = Vin = Vout ( ) ( )2,0,2,0, 22 pTpGS p nTnGS n VV k VVk −=− ( ) ( )2,02,0 22 pTCCin p nTin n VVV k VVk −−=− ( ) R pTCC R nT TH k VV k V V 11 1 ,0,0 + ++ = p n R k kk = Chapter 6 Switching Characteristics of CMOS inverter (Dynamic characteristics) Delay Definitions t Vout Vin input waveform output waveform tp = (tpHL + tpLH)/2 Propagation delay t 50% tpHL 50% tpLH tf 90% 10% tr signal slopes Vin Vout The propagation delay tp of a gate defines how quickly it responds to a change at its input(s). Inverter Transient Response (input step pulse) -0.5 0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5 Vin V ou t( V ) t (sec) x 10-10 VDD=2.5V 0.25µm W/Ln = 1.5 W/Lp = 4.5 Reqn= 13 kΩ (÷ 1.5) Reqp= 31 kΩ (÷ 4.5) tpHL = 36 psec tpLH = 29 psec so tp = 32.5 psec tf trtpHL tpLH From simulation: tpHL = 39.9 psec and tpLH = 31.7 psec Inverter delay, rising Similar calculation as for falling delay Separate into regions where PMOS is in linear, saturation                 − + −− + −−−− = 1 )(4 ln 2 )( ,0 ,0 ,0 ,0 OLOH pTOLOH pTOLOH pT pTOLOHp L PLH VV VVV VVV V VVVk Ct Delay Definitions t Vout Vin input waveform output waveform tp = (tpHL + tpLH)/2 Propagation delay t 50% tpHL 50% tpLH tf 90% 10% tr signal slopes Vin Vout The propagation delay tp of a gate defines how quickly it responds to a change at its input(s). Inverter rise, fall time: approaches Exact method: separate into regions t1 - Vout drops from 0.9VCC to VCC-VT (NMOS in saturation) - Vout rises from 0.1VCC to VT (PMOS in saturation) t2 - Vout drops from VCC-VT to 0.1VCC (NMOS in linear region) - Vout rises from VT to 0.9 VCC (PMOS in linear region) tf,r = t1 + t2 Average current method: Find current at start and end of transition Find average and use avg risefall I VC∆ =,τ Example 6.2 CMOS inverter actual delay What if input has finite rise/fall time?⇒not a step pulse Both transistors are on for some amount of time Capacitor charge/discharge current is reduced 2 2 2 )()(      += rphlphl tinputsteptactualt 2 2 2 )()(       += fplhplh t inputsteptactualt Empirical equations: Example :6.3 Vdd=3.3V, Ln=Lp=0.8µm, Cin=100fF, Wp/Wn=2.75 CMOS design simulation results The smallest transistor has largest propagation delay (why?) Propagation delay simulation results At very short channel width, the delay approaches a limit value of about 0.2nsec , which is mainly determined by technology-specific parameters, independent of extrinsic capacitance component. Inverter delay revisited (Lower Vdd Increases Delay) CL * Vdd I =Td Td(Vdd=5) Td(Vdd=2) = (2) * (5 - 0.7)2 (5) * (2 - 0.7)2 ≈ 4 I ~ (Vdd - Vt) 2 Relatively independent of logic function and style. 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00 5.50 6.00 6.50 7.00 7.50 2.00 4.00 6.00 Vdd (volts) N O R M A L IZ ED D E L A Y adder (SPICE) microcoded DSP chip multiplier adder ring oscillator clock generator 2.0µm technology