Review Sheet for Exam - Computer Architecture | CPSC 5155G, Study notes of Computer Architecture and Organization

Download Review Sheet for Exam - Computer Architecture | CPSC 5155G and more Study notes Computer Architecture and Organization in PDF only on Docsity! What does the following circuit do? More specifically, analyze the circuit and produce its state table and state diagram. Assume that the circuit starts at Y1Y0 = 00. ANSWER: The best way to do this is to proceed mechanically. 1. The first step is to identify all of the inputs and outputs, giving a label to each. This figure has done that. Note that this is not a circuit with output in the sense that a sequence detector has output. It is some sort of counter. 2. Characterize the inputs and outputs of the flip-flops. Show as Boolean expressions. T0 = 1, T1 = Q0’. 3. Construct the Next State and Output Tables. There is no output in the sense of a sequence detector, so we just do the next state tables. Present State Input Next State Input Next State Y0 Y1 T0 Y0(t + 1) T1 Y1(t + 1) 0 0 1 1 1 1 0 1 1 1 1 0 1 0 1 0 0 0 1 1 1 0 0 1 In this form, the table is completely puzzling. We need to produce the final table. A given computer design calls for an 18–bit MAR and an 8–bit MBR. a) How many addressable memory elements can the memory contain? b) How many bits does each addressable unit contain? c) What is the size of the address space in bytes? Comment: The MBR (Memory Buffer Register) is often called the MDR (Memory Data Register). a) The memory can contain 218 = 256K addressable memory elements. b) Each element contains 8 bits, because the MBR has size of 8 bits. The memory contains 256 KB. c) The size of the address space in bytes is 256 KB. Suppose a computer using direct mapped cache has 232 words of main memory and a cache of 1024 blocks, where each cache block contains 32 words. a) How many blocks of main memory are there? b) What is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, block, and word fields? c) To which cache block will the memory reference 0000 63FA map? Recall that 1024 = 210 and 32 = 25. a) The size of a cache block (cache line) is 32 words. The size of a main memory block is also 32 words. The number of blocks is 232 / 25 = 227. b) Memory tag will be 27 bits. Offset in the cache line is 5 bits. The memory tag is split into two parts: 10 bit cache line number 17 bit cache tag. The format of the address is Tag | Cache Line | Offset. The tag contains 17 bits. The cache line is 10 bits. The offset is 5 bits. Bits 31 – 15 14 – 5 4 – 0 Cache View Tag Line Offset Address View Block Number Offset To which cache block will the memory reference 0000 63FA map? The cache line number is contained in bits 14 – 5 of the address. We need the low order 15 bits of the address. Examine the low order 16 bits (4 hexadecimal digits). 63FA 0110 0011 1111 1010 0 1100011111 11010 The cache line is 1100011111 or 0011 0001 1111 = 31F ANDI Microcode The common fetch microcode is as follows. Address Micro-Op B1 B2 B3 ALU M1 M2 S2 = 0 S2 = 1 0x20 0 1 0 2 1 0 8 0x21 0x21 0x21 0 1 1 1 5 0 0 0x22 0x22 0x22 0 0 6 4 2 0 0 0x23 0x23 0x23 1 0 0 0 0 0 0 0x20 0x20 The opcode for ANDI is 0x02. ANDI Op-Code = 00010 IR  B1, R  B2, and, B3  R. Address Micro-Op B1 B2 B3 ALU M1 M2 B = 0 B = 1 0x02 0 4 3 3 7 0 0 0x20 0x20 STR Microcode Begin with the common “start up” microcode, which ends in the dispatch to the microprogram at the correct address. The common fetch microcode is as follows. Address Micro-Op B1 B2 B3 ALU M1 M2 S2 = 0 S2 = 1 0x20 0 1 0 2 1 0 8 0x21 0x21 0x21 0 1 1 1 5 0 0 0x22 0x22 0x22 0 0 6 4 2 0 0 0x23 0x23 0x23 1 0 0 0 0 0 0 0x20 0x20 The next thing to do is to process the indirection. This requires selection of some addresses other than the obvious 0x0D. I have selected 0x32 for the start of the microprogram for STR. This requires that the (S2 = 0) option have address 0x35. Assuming that the op-code for STR is 0x0D, we have this at that address. Address Micro-Op B1 B2 B3 ALU M1 M2 S2 = 0 S2 = 1 0x0D 0 4 3 2 5 0 0 0x35 0x32 Here is the defer code. READ Address Micro-Op B1 B2 B3 ALU M1 M2 S2 = 0 S2 = 1 0x32 0 0 0 0 0 0 8 0x2D 0x2D WAIT Address Micro-Op B1 B2 B3 ALU M1 M2 S2 = 0 S2 = 1 0x33 0 0 0 0 0 0 0 0x2E 0x2E MBR  B2, tra2, B3  MAR Address Micro-Op B1 B2 B3 ALU M1 M2 S2 = 0 S2 = 1 0x34 0 0 6 2 2 0 0 0x2F 0x2F