Understanding Sequential Circuits: Clocked Flip-Flops and their Dependence on Gate Delay -, Study notes of Computer Architecture and Organization

Download Understanding Sequential Circuits: Clocked Flip-Flops and their Dependence on Gate Delay - and more Study notes Computer Architecture and Organization in PDF only on Docsity! Sequential Circuits Sequential circuits are those with memory, also called “feedback”. In this, they differ from combinational circuits, which have no memory. The stable output of a combinational circuit does not depend on the order in which its inputs are changed. The stable output of a sequential circuit usually does depend on the order in which the inputs are changed. We usually focus on clocked sequential circuits, in which the circuit changes state at fixed times in a clock cycle. Clocked circuits are easier to design and understand. All sequential circuits depend on a phenomenon called gate delay. This reflects the fact that the output of any logic gate (implementing a Boolean function) does not change immediately when the input changes, but only some time later. The gate delay for modern circuits is typically a few nanoseconds. Another Circuit Dependent on Gate Delay The following is a statement of the Inverse Law of Boolean Algebra But consider the following circuit and its timing diagram Note that for a short time (one gate delay) we have Z = 1. Views of the System Clock The top view is the “real physical view”. It is seldom used. The middle view reflects the fact that voltage levels do not change instantaneously. Flip–Flops: First Definition We consider a flip–flop as a device that stores a single binary value. We consider only clocked flip–flops. These are devices that change value only at times dictated by a system clock. Technically: an unclocked device is called a latch. only clocked devices are called flip–flops. Denote the present time by the symbol T. Denote the clock period by . Rather than directly discussing the clock period, we merely say that the current time is T after the next clock tick the time is (T + 1) The present state of the flip–flop is often called Q(T) The next state of the flip–flop is often called Q(T + 1) The sequence: the present state is Q(T), the clock “ticks”, the state is now Q(T + 1) Details of a Latch The device on the left is an SR latch. It can be shown that when S = 0 and R = 0, the device does not change state; Q(T + 1) = Q(T). The device on the right is a level–triggered SR flip–flop, better called a clocked SR latch. It can be shown that two sets of conditions cause Q(T + 1) = Q(T) 1. Clock = 0 2. Clock = 1 and S = 0 and R = 0. The “clock input” to a flip–flop is so called because it is usually connected to a signal generated in part by the system clock. You instructor likes to call the signal “wake up” or some such. When the signal is asserted, the flip–flop responds to its input. SR Flip–Flop We now abandon the detailed view of flip–flops and adopt a functional view. How does the next state depend on the present state and input. A flip–flop is a “bit holder”. Here is the diagram for the SR flip–flop. Here is the state table for the SR flip–flop. S R Q(T + 1) 0 0 Q(T) 0 1 0 1 0 1 1 1 Error Note that setting both S = 1 and R = 1 causes the flip–flop to enter a logically inconsistent state, followed by an indeterministic, almost random, state. For this reason, we label the output for S = 1 and R = 1 as an error. JK Flip–Flop A JK flip–flop generalizes the SR to allow for both inputs to be 1. Here is the characteristic table for a JK flip–flop. J K Q(T + 1) 0 0 Q(T) 0 1 0 1 0 1 1 1  TQ Note that the flip–flop can generate all four possible functions of a single variable: the two constants 0 and 1 the variables Q and Q . The D Flip–Flop The D flip–flop specializes either the SR or JK to store a single bit. It is very useful for interfacing the CPU to external devices, where the CPU sends a brief pulse to set the value in the device and it remains set until the next CPU signal. The characteristic table for the D flip–flop is so simple that it is expressed better as the equation Q(T + 1) = D. Here is the table. D Q(T + 1) 0 0 1 1