Understanding Sequential Circuits: Latches and Flip-Flops - Prof. Zhijie Shi, Study notes of Computer Science

Download Understanding Sequential Circuits: Latches and Flip-Flops - Prof. Zhijie Shi and more Study notes Computer Science in PDF only on Docsity! Sequential Circuits: Latches and Flip-Flops Z. Jerry Shi Computer Science and Engineering University of Connecticut Thank John Wakerly for providing his slides and figures. Sequential circuits • Output depends on current input and past history of inputs • The circuits can remember past inputs – “Memory” to remember state between two inputs How can you tell an input combination is current or past? Bistable element • The simplest sequential circuit • Two states – One state variable, say, Q HIGH LOW LOW HIGH Bistable element • The simplest sequential circuit • Two states – One state variable, say, Q LOW HIGH HIGH LOW Analog analysis • Assume pure CMOS thresholds, 5 V rail • Theoretical threshold center is 2.5 V Metastability • Metastability is inherent in any bistable circuit • Two stable points one metastable point , Control bistable • How to control it? – Control inputs S and R • S-R latch S-R latch operation Metastability is possible if S and R are negated simultaneously. S-R latch using NAND gates S_L orS Q R_L QN orR S_L R_L Q QN 0 0 1 1 0 1 1 0 1 0) 0 1 1 1 lastQ last QN S-R latch with enable Let C decide whether S and R can reach the bistable circuit. D latch c D Q QN 10 0 { Pp 8 1 1 1 fe) C ao 0 x lastQ last QN D —»—_______] QN Positive edge-triggered D flip-flop 1 2 CLK_L QLatch 2 Status QMLatch 1 Status CLK Dprev@ ↑Dprev@ ↑↑↓ 0 QM=Dprev@ ↑EnabledDprev@ ↑Disabled1 Dprev@ ↑D Dprev@ ↑Disabled~ DEnabled ↓ 1 ↑ 0 QM = D @ ↑Enabled↑D@ ↑Disabled01 Positive edge-triggered D flip-flop behavior CLK QM ( QN \ / CLK Q QN D 0 4 0 1 — 0 Qy— 1 x x ee 0 —> CLK afo- Oo lastQ last QN 1 lastQ last ON D flip-flop timing parameters • Propagation delay (from CLK) • Setup time (D before CLK) • Hold time (D after CLK) TTL positive edge-triggered D commercial circuit (x74) • Preset and clear inputs • 3 feedback loops – interesting analysis (Sec. 7.9) • Light loading on D Negative edge-trigged D flip-flop * Invert the input CLK signal Da D Q D Q-—1Q 0 1 0 1 1 1 1 0 —D Qke— x 0 lastQ last QN -OP clk alo- x 1 lastQ last QN Positive-edge-triggered D flip-flop with enable (a) D How does EN works? “T= > 4} Stk alo-t-o an (b CLK & D ENCLK @Q QN —lpb Que Oo 1 0 4 St _ten 11 fF 1 0 pete 2fo- x O J last Q last QN x xX Q. lastQ last QN x xX 1 last Q last QN Edge-Triggered J-K flip-flop • Not used much anymore • Don’t worry about them Master/slave J-K flip-flop (pulse triggered) M | 5 o SVS of tna Cc c QM_L Ki ) PR 20— R QO ON Co I, J > J eK oC Q QN x x 0 lastQ last QN —SJ 70 0 60 lastQ last QN —c¢ ~ —_Ik 191O- 0 1 UL 0 1 1 OL 1 0 1 1 | L last QN lastQ Timing diagram of master/slave J-K flip-flop Ignored Ignored Ignored Ignored Ignored since C is 0. since QN is 0. ( since Cisnow0O. _ since QisO. since QN is 0. J ~ Sf K /\ QM QM_L QN T flip-flops with enable ¢ Important for counters — EN Q EN O—*—_ To HH Q (>—_1 ON Many types of latches and flip-flops • S-R latch • S_L-R_L latch • S-R latch with enable • D latch • Edge-triggered D flip-flop • Edge-triggered D flip-flop with enable • Edge-triggered D flip-flop with preset and clear S fli fl• can p- op • Edge-triggered J-K flip-flop • Master/slave S-R flip-flop • Master/slave J-K flip-flop • T flip-flop • T flip-flop with enable