Download Understanding Sequential Circuits: Latches and Flip-flops - Prof. Maciej Ciesielski and more Assignments Engineering in PDF only on Docsity! Maciej Ciesielski Department of Electrical and Computer Engineering 10/27/2008 Engin112 – Lectures 23,24 Sequential Circuits Latches and Flip-flops 10/27/2008 Engin 112 - Intro to ECE 2 Sequential vs Combinational Ckts Recall definition of combinational logic Outputs are a function of inputs Combinational delay (each gate has some propagation delay) Sequential circuits Outputs depend on inputs and previous values of outputs » Outputs depend on previous state of the circuit » State is stored in memory elements (registers, latches, fliplops) 10/27/2008 Engin 112 - Intro to ECE 5 Synchronous Sequential Circuits Synchronous sequential circuits Storage elements change only at discrete instances of time Timing controlled by “clock” Clock generator provides train of clock pulses: Clocked (synchronous) sequential circuit: 10/27/2008 Engin 112 - Intro to ECE 6 Storage Elements Binary storage device capable of storing one bit Latch = level-sensitive device State changes with input when enabled (e.g., when clock = 1) Holds last input value when disabled (when clock = 0) Flip-flop = edge-triggered device State of flip-flop can only change during clock transition Example: Flip-flops change on rising/falling edge of clock Why change on an edge? Couldn’t we change state while clock is 1? That would be a latch! Edge is moment in time, state is duration Feedback would continue during clock being 1, causing possible race conditions 10/27/2008 Engin 112 - Intro to ECE 7 Level-sensitive vs Edge-triggered Latches are level-sensitive Flip-flops are edge-sensitive 10/27/2008 Engin 112 - Intro to ECE 10 SR Latch - Operation Operation: What happens if both S,R = 1? Both NOR outputs become 0 Unstable state after releasing S and R R,S=0 Q=1 Q’=0 R=1 Q=0 Q’=1 R,S=0 Q=0 Q’=1 S=1 Q=1 Q’=0 10/27/2008 Engin 112 - Intro to ECE 11 SR Latch with NAND Gates Latch can also be implemented with NAND gates Input of 0 indicates set or reset Referred to as S’R’ latch or SR latch 10/27/2008 Engin 112 - Intro to ECE 12 SR Latch with Control Input We want to control when latch can change Extra control input En (enable) SR latch with control input Problem: indeterminate state for S=R=1, when En=1 Circuit: NAND gates and S’R’ latch 10/27/2008 Engin 112 - Intro to ECE 15 D Latch Operation Show the output for this D latch Q C C D Q D En 10/27/2008 Engin 112 - Intro to ECE 16 Latch Symbols Graphic symbols for latches: 10/27/2008 Engin 112 - Intro to ECE 17 D Latch - Summary D latch circuit Data is stored while clock is high How can we build a flip-flop that stores on edge transition? or 10/27/2008 Engin 112 - Intro to ECE 20 Edge Triggering D flip-flop: Q is set to D on falling clock edge While clock is high, D is propagated to Y Q is not effected because C’ is low When C’ goes high, Y propagates to Q 10/27/2008 Engin 112 - Intro to ECE 21 D Flip-Flop Requires 2 D latches and one inverter More efficient implementation: Operation: If CLK=0, then S=R=1 » Q remains stable If CLK=1 and D=0, then R=0 » Q is reset to 0 » Q remains 0 independent of D If CLK=0, then S=R=1 If CLK=1 and D=1, then S=0 » Q is set to 1 » Q remains 1 independent of D Is this flip-flop positive or negative edge triggered? 10/27/2008 Engin 112 - Intro to ECE 22 D Flip-Flop - Operation More efficient implementation: If CLK=0, then S=R=1 » Q remains stable = Q-1 regardless of D (= x) If CLK=1 and D=0, then R=0 » Q is reset to 0 If CLK=1 and D=1, R=0 » Q = 0 If CLK=0, then S=R=1 » Q remains 0 independent of D If CLK=1 and D=1, then S=0 » Q is set to 1 » remains 1 independent of D Is this flip-flop positive or negative edge triggered? Q-1,0 0,0,1 Q’-1,1 1,1,0 x,0 0,1,1 x’,1 1,0,0 x,0 1,1,1 0,1 1,0,1 1,1 1,1,0 1,0 0,1,1 x’,1 1,0,0
