VLSI Principles: Sequential Logic Design and Memory Elements, Study notes of Theatre

Download VLSI Principles: Sequential Logic Design and Memory Elements and more Study notes Theatre in PDF only on Docsity! Lecture 15, ECE 124A, VLSI Principles Kaustav Banerjee ECE 124A VLSI Principles Lecture 15 Sequential CMOS Logic Design-I Prof. Kaustav Banerjee Electrical and Computer Engineering E-mail: kaustav@ece.ucsb.edu Lecture 15, ECE 124A, VLSI Principles Kaustav Banerjee Designing Sequential Logic Circuits Lecture 15, ECE 124A, VLSI Principles Kaustav Banerjee Classification of Memory Elements Static Memory: preserves state as long as power is ON built by using positive feedback or regeneration where the circuit consists of intentional connections between the output and input of a combinational circuit most useful when register will not be updated for extended periods of time (eg., configuration data loaded at power-up time). Condition also holds for most processors that use conditional clocking, (gated CLK) where the CLK is turned off for unused modules----no guarantee on how frequently the registers will be clocked and static memories are needed to state information. bistable element is the most popular form Lecture 15, ECE 124A, VLSI Principles Kaustav Banerjee Dynamic Memory: store data for short (ms) period of time based on the principle of temporary charge storage on parasitic capacitors in MOS devices similar to dynamic logic….. capacitors need to be refreshed periodically to compensate for charge leakage significantly simpler----hence, provide higher performance and lower power dissipation most useful in datapath circuits that require higher performance levels and are periodically clocked Classification of Memory Elements Lecture 15, ECE 124A, VLSI Principles Kaustav Banerjee Naming Conventions Definitions: a latch is a level sensitive device a register is an edge-triggered storage element There are many different naming conventions For instance, many books call edge-triggered elements flip-flops This may lead to confusion however… Any bistable component formed by the cross coupling of gates is a flip-flop (FF) Lecture 15, ECE 124A, VLSI Principles Kaustav Banerjee Timing of P/N Latches In clk In Out Positive Latch CLK D G Q Out Out stable Out follows In In clk In Out Negative Latch CLK D G Q Out Out stable Out follows In When clk is high… When clk is low… Lecture 15, ECE 124A, VLSI Principles Kaustav Banerjee Latch versus Register Latch stores data when clock is low (or high) D Clk Q D Clk Q Register stores data when clock rises (or falls) Clk Clk D D Q Q Lecture 15, ECE 124A, VLSI Principles Kaustav Banerjee Characterizing Timing Clk D Q tC 2 Q Clk D Q tC 2 Q tD 2 QRegister Latch Requires an extra timing parameter…Data is ready when Clk arrives…. Data may arrive after Clk edge…. Lecture 15, ECE 124A, VLSI Principles Kaustav Banerjee Maximum Clock Frequency To ensure that the input data of the sequential elements is held long enough after the CLK edge and is not modified too soon by the new wave of data coming in: 2) tcdreg + tcdlogic > thold tcd: contamination delay = minimum delay1) Tmin = tclk-Q + tp,comb + tsetup FF ’s LOGIC tp,comb φ Register D Q CLK Edge tsetup thold Clk period must accommodate the longest delay of any stage in the network Lecture 15, ECE 124A, VLSI Principles Kaustav Banerjee Static Memories use Positive Feedback: Bi-Stability Vi1 Vo2 Vo2 = Vi 1 Vo1 = Vi 2 V o 1 V i 2 5 V o 1 V i 2 5 V o 1 Vi1 A C B Vo2 Vi1 = Vo2 Vo1 Vi2 Vi2 = Vo1 Static Latches and Registers A, B, and C are the only three possible operating points If gain>1 in the transient region: A and B are the only stable operating points, C is a metastable point Obtained by flipping the VTC of the second inverter w.r.t origin and then rotating anti-clkwise by 900 VTC of INV1 VTC of INV2 Lecture 15, ECE 124A, VLSI Principles Kaustav Banerjee Meta-Stability in Bi-Stable Circuits • Gain is larger than 1 in the transition region • Every small deviation causes the operation point to move away from its original bias point, C ---metastable A C d B V i2 5 V o1 Vi1 5 Vo2 A C d B V i2 5 V o1 Vi1 5 Vo2= = 3. Deviation is amplified by the gain of the first inverter and then further amplified by the second inverter 4. The bias point moves away from C until one of the operation points A or B is reached A: Vi1=0, Vi2=1 = 1. Apply small deviation d to Vi1 biased at C 2. Deviation gets amplified and regenerated around the circuit loop At A and B the loop gain is much smaller than 1…hence, stable points =