VHDL: Understanding Concurrent and Sequential Data Processing and Assignments, Slides of Computer Science

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Sequential VHDL • Concurrent and sequential data processing • Signal and variable assignment • Process statement – Combinational process – Clocked process • If statement • Case statement • Multiple statement • Null statement • Wait statement Docsity.com Concurrent and sequential data processing • Designing sequential processes presents a new design dimension to hardware designers who have worked at gate level • First we look at concurrent and sequential data processing • The difference between sequential and concurrent assignment is important to understand • Electronics are parallel by nature • In practice, all the gates in a circuit diagram can be seen as concurrently “executing” units • In VHDL there are language constructions which can handle both concurrent and sequential data processing • Many of the VHDL commands are only valid in the concurrent or sequential part of VHDL Docsity.com VHDL commands being valid in both the concurrent and the sequential parts • Signal assignment • Declaration of types and constants • Function and procedure calls • Assert statement • After delay • Signal assignment Docsity.com Use of commands • It is important to know where the various VHDL commands can be used and where the VHDL code is concurrent or sequential • In brief, it can be said that the VHDL code is concurrent throughout the architecture except for in processes, functions and procedures architecture rtl of ex is concurrent declaration part begin concurrent VHDL process (...) sequential declaration part begin sequential VHDL end process; concurrent VHDL end; Process, one concurrent statement Docsity.com Comparison of signal and variable assignment • Signals and variables are used frequently in VHDL code, but they represent completely different implementations. • Variables are used for sequential execution like other algorithmic programs, while signals are used for concurrent execution. • Variable and signal assignment are differentiated using the symbols “:=“ and “<=“ • A variable can only be declared and used in the sequential part of VHDL. • Signals can only be declared in the concurrent part of VHDL but can be used in both the sequential and concurrent parts. • A variable can be declared for exactly the same data types as a signal. • It is also permissible to assign a variable the value of a signal and vice versa, provided that they have the same data type. • The big difference between a signal and a variable is that the signal is only assigned its value after a delta delay, while the variable is given its value immediately. Docsity.com Differences between signal and variable processing • The lines in the sequential VHDL code are executed line by line – That is why it is called sequential VHDL • In concurrent VHDL code, the lines are only executed when an event on the sensitivity list occurs – This sensitivity list is explicit in case of process – Anyway the sensitivity list means the Docsity.com Differences between signals and variables • Sum1 and sum2 are signals p0: process begin wait for 10 ns; sum1<=sum1+1; sum2<=sum1+1; end process; Time Sum1 Sum2 Sum1 Sum2 0 0 0 0 0 10 0 0 1 2 10 + ∆ 1 1 1 2 20 1 1 2 3 20 + ∆ 2 2 2 3 30 2 2 3 4 30 + ∆ 3 3 3 4  Sum1 and sum2 are variables p1: process variable sum1, sum2: integer; begin wait for 10 ns; sum1:=sum1+1; sum2:=sum1+1; end process; Docsity.com Information transfer • Variables cannot transfer information outside the sequential part of VHDL in which it is declared, in the previous example process p1. • If access is needed to the value of sum1 or sum2, they must be declared as signals or the value of the variable assigned to a signal. Entity ex is port(sum1_sig, sum2_sig: out integer); end; Architecture bhv of ex is begin p1: process variable sum1, sum2: integer; begin wait for 10 ns; sum1:=sum1+1; sum2:=sum1+1; sum1_sig<=sum1; sum2_sig<=sum2; end process; end;  VHDL-87: Variables can only store temporally values inside a process, function or procedure.  VHDL-93: Global shared variables have been introduced which can transfer information outside the process. Docsity.com Example to test the “wait until” command - circuit description entity cir is port (a,clk: in bit; y: out bit); end; architecture bhv of cir is begin process begin Docsity.com Example to test the “wait until” command - stimulus generator entity stm is port (a,clk: out bit; y: in bit); end; architecture dtf of stm is begin a<='1' after 20 ns, '0' f 25 Docsity.com Example to test the “wait until” command - test bench I entity bnc is end; use std.textio.all; Architecture str of bnc is Component cir port (a,clk:in bit;y:out bit); end Component; Component stm port (a,clk:out bit;y:in bit); end Component; for all:cir use entity work cir(bhv); Docsity.com Example to test the “wait until” command - simulation result # Loading c:\_vhdl\bin\lib\std.stan dard # Loading c:\_vhdl\bin\lib\std.texti o # Loading c:\_vhdl\bin\lib\work.bn c(str) Docsity.com Example to test the “wait until” command - simulation result # 0 ns 0 0 0 # TIME a clk y # 10 ns 0 1 0 # 20 ns 1 1 0 # 25 ns 0 1 0 Docsity.com Qualified expression • In some contexts, an expression involving an overloaded item may need to be qualified – So that its meaning may be unambiguous • An expression is qualified by enclosing the expression in parentheses and prefixing the parenthesised expression with the name of a type and a tic (‘) • Consider the following procedures declarations: – procedure to_integer (x: in character; y: inout integer); – procedure to_integer (x: in bit; y: inout integer); • The procedure call to_integer (‘1’, n) is ambiguous • Solution: to_integer (character’(‘1’), n); or to_integer (bit’(‘1’), n); Docsity.com Process execution • Once the process has started, it takes the time ∆ time (the simulator’s minimum resolution) for it to be moved back to Waiting state • This means that no time is taken to execute the process • A process should also be seen as an infinite loop between begin and end process; Docsity.com An example for the process operation • The process is started when the signal clk goes low. • It passes through two statements and waits for the next edge. • The programmer does not have to add loop in the process: it will restart from the beginning in any PROCESS C_out CLK A_in B_in D_out start sync_process: process begin wait until clk=‘0’; c_out<= not (a_in and b_in); d_out <= not b_in; end process; Docsity.com Modeling the process delay • In practice the statements will take a different length of time to implement. • This delay in the process can be modeled as follows: c_out<= not (a_in and b_in) after 20 ns; d_out<= not a_in after 10 ns; • This means that c_out will be affected 20 ns and d_out 10 ns after the start of the process. • The simulator will place the result in a time event queue for c out and d out: Docsity.com Example for a combinational process • Example: process (a,b,c) begin d<= (a and b) or c; end process; C A B D  The synthesis result: Docsity.com Incomplete combinational process  In the case of design with combinational processes, all the output signals from the process must be assigned a value each time the process is executed.  If this condition is not satisfied, the signal retain its value.  The synthesis tool will perceive and resolve this requirement by inferring a latch for the output which is not assigned a value throughout the process.  The latch will be closed when the old value for the signal has to be retained.  Functionally, the VHDL code and the hardware will be identical.  But the aim of a combinational process is to generate combinational logic.  If latches are inferred, the timing deteriorate with increased number of gates.  What is more, the latch will normally break the test rules for generating automatic test vectors.  Processes will give rise to latches by mistake are called incomplete combinational processes.  The solution is simple: include all the signals which are “read” inside the process in the sensitivity list for combinational processes. Docsity.com Clocked process • Clocked processes are synchronous and several such processes can be joined with the same clock. • No process can start unless a falling edge occurs at the clock (clk), if the clocking is: wait until clk=‘0’; • This means that data are stable when the clock starts the processes, and the next value is laid out for the next start of the processes. Example Docsity.com Flip-flop synthesis with clocked signals • Clocked processes lead to all the signals assigned inside the process resulting in a flip-flop. • This example shows how a clocked process is translated into a flip-flop. • As figure shows, d_in is translated to d_out with 1 ns delay When it has been synthesized the ex: process begin wait until clk=‘1’; d_out<= d_in after 1 ns; end process; FD D_out D_in CLK D Q CLK Docsity.com Flip-flop synthesis with variables • Variables can also give rise to flip-flops in a clocked process. • If a variable is read before it is assigned a value, it will result in a flip-flop for the variable. • In this example with variable count the synthesis result will ex: process variable count: std_logic_vector (1 downto 0); begin wait until clk=‘1’; count:=count + 1; if count=“11” then q<=‘1’; else q<=‘0’; end if; end process; Docsity.com Testable flip-flop synthesis • If a signal is not assigned a value in a clocked process, the signal will retain the old value. • The synthesis will result a feedback of the signal d from the output ex1: process begin wait until clk=‘1’; if en=‘1’ then q<=d; end if; end process; Q CLK D QB CLK Q D EN select 1 0 MUX Docsity.com If statement • if_statement::=[if_label:] if condition then sequence_of_statements { elsif condition then sequence_of_statements } [ else sequence_of_statements ] end if [ if _label ] ; • Example: if a > 0 then b := a ; else b := abs (a+1) ; Docsity.com Multiplexor modeling with if statement The synthesis result: if sel=‘1’ then c<=b; else c<=a; end if; B SEL select MUX C A Docsity.com Case statement • case_statement ::= [ case _label : ] case expression is case_statement_alternative { case_statement_alternative } end case [ case _label ]; • Example: case a is when '0' => q <= "0000" after 2 ns ; when '1' => q <= "1111" after 2 ns ; end case; Docsity.com Simulation example of “others” - architecture architecture bhv of cir is begin p1: process(a) begin case a is when 0 => q<=3; when 1 | 2 => q<=2; Docsity.com Simulation example of “others” - stimulus generator entity stm is port (a: out integer range 0 to 30; q: in integer range 0 to 6); end; architecture dtf of stm is begin a<=0 after 10 ns, 1 after 20 ns, 6 after 30 ns, 2 after 40 ns, 0 after 50 ns, 10 after 60 ns; end; Docsity.com Simulation example of “others” - test bench I entity bnc is end; use std.textio.all; architecture str of bnc is component cir port (a:in integer range 0 to 30;q:out integer range 0 to 6); end component; component stm port (a:out integer range 0 to 30;q:in integer range 0 to 6); end component; for all:cir use entity work.cir(bhv); Docsity.com Simulation example of “others” - result # time a q aid # ================= ======= # 0 ns 0 3 TRUE # 20 ns 1 3 TRUE # 20 ns 1 Docsity.com Use of range • It is permissible to define ranges in the choice list • This can be done using to and downto • entity case_ex2 is port (a: in integer range 0 to 30; q: out integer range 0 to 6); end; architecture rtl of case_ex2 is begin p1: process(a) begin case a is Docsity.com Use of vectors - bad solution • It is not permissible to define a range with a vector, as a vector does not have a range. • Example (bad): E R R O R ! entity case_ex3 is port (a: in std_logic_vector(4 downto 0); q: out std_logic_vector(2 downto 0)); end; architecture rtl of case_ex3 is begin p1: process(a) begin case a is when “00000” =>q<=“011”; Docsity.com Use of concatenation applying variable • The solution is either to introduce a variable in the process to which the value a & b is assigned or to use what is known as a qualifier for the subtype. • entity case_ex6 is port (a,b: in std_logic_vector(2 downto 0); q: out std_logic_vector(2 downto 0)); end; architecture rtl of case_ex6 is begin p1: process(a,b) variable int: std_logic_vector (5 downto 0); begin int := a & b; case int is when “000000” =>q<=“011”; when “001110” =>q<=“010”; when others =>b<=“000”; end case; Docsity.com Use of concatenation applying qualifier • entity case_ex7 is port (a,b: in std_logic_vector(2 downto 0); q: out std_logic_vector(2 downto 0)); end; architecture rtl of case_ex7 is begin p1: process(a,b) subtype mytype is std_logic_vector (5 downto 0); begin case mytype’(a & b) is when “000000” =>q<=“011”; when “001110” =>q<=“010”; when others =>b<=“000”; end case; end process; end; Docsity.com Multiple assignment • In the concurrent part of VHDL you are always given a driver for each signal assignment, which is not normally desirable. • In the sequential part of VHDL it is possible to assign the same signal several times in the same process without being given several drivers for the signal. • This method of assigning a signal can be used to assign signals a default value in the process. • This value can then be overwritten by another signal assignment. • The following two examples are identical in terms of both VHDL simulation and the synthesis result. Docsity.com Null statement null_statement::= [ label : ] null ; • The null - statement explicitly prevents any action from being carried out. • This statement means “do nothing”. • This command can, for example, be used if default signal assignments have been used in a process and an alternative in the case statement must not change that value. Docsity.com Null statement - example • architecture rtl of ex is begin p1: process (a) begin q1<=“0”; q2<=‘0’; q3<=‘0’; case a is when “00” => q1<=“1”; when “10” => q2<=‘1’; q3<=‘1’; when others => null; end case; end process; end; Docsity.com Null statement - conclusions • In the previous example, null could have been left out. • Readability is increased if the null statement is included. • If null is omitted, there is a risk that, if someone else reads the VHDL code, they will be uncertain whether the VHDL designer has forgotten to make a signal assignment or whether the line should be empty. Docsity.com Features of the wait statement • In the first example the process will be triggered each time that signal a or b changes value (a’event or b’event) • Wait on a,b; has to be placed at the end of the second example to be identical with the first example because all processes are executed at stat-up until they reach their first wait statement. • That process also executed at least once, which has sensitivity list and there is no changes in the values of the list members Docsity.com Details of the wait’s types • Wait until a=‘1’; means that, for the wait condition to be satisfied and execution of the code to continue, it is necessary for signal a to have an event, i.e. change value, and the new value to be ‘1’, i.e. a rising edge for signal a. • Wait on a,b; is satisfied when either signal a or b has an event (changes value). • Wait for 10 ns; means that the simulator will wait for 10 ns before continuing execution of the process. – The starting time point of the waiting is important and Docsity.com Examples of wait statement • type a: in bit; c1, c2, c3, c4, c5, c6, c7: out bit; Example 1 process (a) begin c1<= not a; end process; Example 2 process begin c2<= not a; wait on a; end process; Example 3 process begin wait on a; c3<= not a; end process; Example 4 process begin wait until a=‘1’; c4<= not a; end process; Example 5 process begin c5<= not a; wait until a=‘1’; end process; Example 6 process begin c5<= not a; wait for 10 ns; end process; Example 7 process begin c5<= not a; wait until a=‘1’ for 10 ns; end process; Docsity.com An Example S R Q Qb 1 0 0 1 0 1 1 0 0 0 1 1 1 1 ? ? Combinational Sequential Entity rsff is Port ( set,reset: IN Bit; q,qb : INOUT Bit); End rsff; Architecture netlist of rsff is Component nand2 port (a,b : in bit; c: out bit); End component Begin U1 : port map (set,qb,q); U2 : port map (reset,q,qb); End first; Architecture sequential of rsff is Begin Process(set,reset) Begin If set=‘1’ and reset = ‘0’ then q<=‘0’ after 2ns; qb <= ‘1’ after 4ns; elseif set=‘0’ and reset = ‘1’ then q<=‘1’ after 4ns; qb <= ‘0’ after 2ns; elseif set=‘0’ and reset = ‘0’ then q<=‘1’ after 2ns; qb <= ‘1’ after 2ns; Endif; End process; End first; Set Reset Q Qb Docsity.com Synthesis Example Entity 3add is Port ( a,b,c: std_logic; z: out std_logic); End 3add; Architecture first of 3add is Begin z<= a and b and c; End first; Architecture second of 3add is Begin Process (a,b,c) Variable temp:std_logic; Begin temp := b and c; z <= a and var; End; End second; a b c z b c z a Docsity.com Synthesis Example • A concurrent signal assignment that requires sequential hardware Entity 3sel is Port ( a,b,c: std_logic; z: out std_logic); End 3sel; Architecture cond of 3add is Begin z<= a when b=‘1’ else b when c=‘1’ else z; End first; z c a b Q R C D Latch Docsity.com