Understanding Level-Sensitive D Latches, D Flip-Flops, and FSMs in Digital Design, Study notes of Computer Science

Download Understanding Level-Sensitive D Latches, D Flip-Flops, and FSMs in Digital Design and more Study notes Computer Science in PDF only on Docsity! 1 Digital Design Copyright © 2006 Frank Vahid Digital Design Chapter 3: Sequential Logic Design -- Controllers Slides to accompany the textbook Digital Design, First Edition, by Frank Vahid, John Wiley and Sons Publishers, 2007. http://www.ddvahid.com Modified by Jay Brockman, University of Notre Dame, 2007 Copyright © 2007 Frank Vahid Instructors of courses requiring Vahid's Digital Design textbook (published by John Wiley and Sons) have permission to modify and use these slides for customary course-related activities, subject to keeping this copyright notice in place and unmodified. These slides may be posted as unanimated pdf versions on publicly-accessible course websites.. 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Instructors may obtain PowerPoint source or obtain special use permissions from Wiley – see http://www.ddvahid.com for information. 2 Digital Design Copyright © 2006 Frank Vahid Introduction • Sequential circuit – Output depends not just on present inputs (as in combinational circuit), but on past sequence of inputs • Stores bits, also known as having “state” – Simple example: a circuit that counts up in binary • In this chapter, we will: – Design a new building block, a flip-flop, that stores one bit – Combine that block to build multi-bit storage – a register – Describe the sequential behavior using a finite state machine – Convert a finite state machine to a controller – a sequential circuit having a register and combinational logic 3.1 si z e ansi Combinational digital circuit 1 a b 1 F0 1 a b ? F0 Must know sequence of past inputs to know output Sequential digital circuit Note: Slides with animation are denoted with a small red "a" near the animated items 3 Digital Design Copyright © 2006 Frank Vahid Example Needing Bit Storage • Flight attendant call button – Press call: light turns on • Stays on after button released – Press cancel: light turns off – Logic gate circuit to implement this? QCall Cancel Doesn’t work. Q=1 when Call=1, but doesn’t stay 1 when Call returns to 0 Need some form of “feedback” in the circuit a a 3.2 Bit Storage Blue lightCall button Cancel button 1. Call button pressed – light turns on Bit Storage Blue lightCall button Cancel button 2. Call button released – light stays on Bit Storage Blue lightCall button Cancel button 3. Cancel button pressed – light turns off Types of Storage Elements set reset out data_in data_out write set-reset latch (SR latch) data latch (D latch) Jay Brockman, 2007 Feedback-Based Storage • How do you get the data in and out? Jay Brockman, 2007 MUX Based Latches Q D clk 0 1 Positive Latch Q D clk 1 0 Negative Latch Q = !clk & Q | clk & DQ = clk & Q | !clk & D feedback transparent when the clock is low transparent when the clock is high feedback • Change the stored value by cutting the feedback loop [Adapted from Mary Jane Irwin and Vijay Narananan, adaptation of Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.] SR Latch disallowed0011 reset1010 set0101 memory!QQ00 !QQRS S R Q !Q [Adapted from Mary Jane Irwin and Vijay Narananan, adaptation of Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.] 8 Digital Design Copyright © 2006 Frank Vahid Example Using SR Latch for Bit Storage • SR latch can serve as bit storage in previous example of flight-attendant call button – Call=1 : sets Q to 1 • Q stays 1 even after Call=0 – Cancel=1 : resets Q to 0 • But, there’s a problem... R S Q Call but ton Blue light Cancel but ton Bit Storage Blue lightCall but ton Cancel but ton 17 Digital Design Copyright © 2006 Frank Vahid D Flip-Flop • Solves problem of not knowing through how many latches a signal travels when C=1 – In figure below, signal travels through exactly one flip-flop, for Clk_A or Clk_B – Why? Because on rising edge of Clk, all four flip-flops are loaded simultaneously -- then all four no longer pay attention to their input, until the next rising edge. Doesn’t matter how long Clk is 1. Two latches inside each flip-flop D1 Q1 D2 Q2 D3 Q3 D4 Q4Y Clk Clk_A Clk_B T w o l a t ches insde ach fli p -flop 18 Digital Design Copyright © 2006 Frank Vahid D Latch vs. D Flip-Flop • Latch is level-sensitive: Stores D when C=1 • Flip-flop is edge triggered: Stores D when C changes from 0 to 1 – Saying “level-sensitive latch,” or “edge-triggered flip-flop,” is redundant – Two types of flip-flops -- rising or falling edge triggered. • Comparing behavior of latch and flip-flop: Clk D Q (D latch) Q (D flip-flop) 10 87 654 9 3 1 2 19 Digital Design Copyright © 2006 Frank Vahid Flight-Attendant Call Button Using D Flip-Flop • D flip-flop will store bit • Inputs are Call, Cancel, and present value of D flip-flop, Q • Truth table shown below Preserve value: if Q=0, make D=0; if Q=1, make D=1 Cancel -- make D=0 Call -- make D=1 Let’s give priority to Call -- make D=1 Circuit derived from truth table, using Chapter 2 combinational logic design process Call but ton Cancel but ton Flight attendant call-button system Blue light D Q’ QClk Call but ton Cancel but ton Blue light Call Cancel Q 20 Digital Design Copyright © 2006 Frank Vahid Basic Register • Typically, we store multi-bit items – e.g., storing a 4-bit binary number • Register: multiple flip-flops sharing clock signal – From this point, we’ll use registers for bit storage • No need to think of latches or flip-flops • But now you know what’s inside a register D Q D Q D Q D Q I2I3 Q2Q3 Q1 Q0 I1 I0 clk 4-bit register I3 I2 I1 I0 Q3 Q2 Q1 Q0 reg(4) 21 Digital Design Copyright © 2006 Frank Vahid Example Using Registers: Temperature Display • Temperature history display – Sensor outputs temperature as 5-bit binary number – Timer pulses C every hour – Record temperature on each pulse, display last three recorded values a4x4 x3 x2 x1 x0 C a3 a2 a1 a0 t emp r a tu r e senor timer Display Present b4 b3 b2 b1 b0 Display TemperatureHistoryStorage 1 hour ago c4 c3 c2 c1 c0 Display 2 hours ago (In practice, we would actually avoid connecting the timer output C to a clock input, instead only connecting an oscillator output to a clock input.) 22 Digital Design Copyright © 2006 Frank Vahid Example Using Registers: Temperature Display • Use three 5-bit registers 15 18 20 0 0 0 18 0 0 21 18 0 24 21 18 25 24 21 26 25 24 27 26 25 21 21 22 24 24 24 25 25 26 26 26 27 27 27 27x4...x0 C Ra Rb Rc Q4 C x4 x3 x2 x1 x0 Q3 Q2 Q1 Q0 Ra Rb I4 I3 I2 I1 I0 Q4 a4 a3 a2 a1 a0 Q3 Q2 Q1 Q0 I4 I3 I2 I1 I0 Rc Q4 b4 b3 b2 b1 b0 Q3 Q2 Q1 Q0 I4 I3 I2 I1 I0 c4 c3 c2 c1 c0 TemperatureHistoryStorage 23 Digital Design Copyright © 2006 Frank Vahid Finite-State Machines (FSMs) and Controllers • Want sequential circuit with particular behavior over time • Example: Laser timer – Push button: x=1 for 3 clock cycles – How? Let’s try three flip-flops • b=1 gets stored in first D flip-flop • Then 2nd flip-flop on next cycle, then 3rd flip-flop on next • OR the three flip-flop outputs, so x should be 1 for three cycles 3.3 Controller x b clk laser patient D Q D Q D Q clk b x 24 Digital Design Copyright © 2006 Frank Vahid Need a Better Way to Design Sequential Circuits • Trial and error is not a good design method – Will we be able to “guess” a circuit that works for other desired behavior? • How about counting up from 1 to 9? Pulsing an output for 1 cycle every 10 cycles? Detecting the sequence 1 3 5 in binary on a 3-bit input? – And, a circuit built by guessing may have undesired behavior • Laser timer: What if press button again while x=1? x then stays one another 3 cycles. Is that what we want? • Combinational circuit design process had two important things 1. A formal way to describe desired circuit behavior • Boolean equation, or truth table 2. A well-defined process to convert that behavior to a circuit • We need those things for sequence circuit design 25 Digital Design Copyright © 2006 Frank Vahid Describing Behavior of Sequential Circuit: FSM • Finite-State Machine (FSM) – A way to describe desired behavior of sequential circuit • Akin to Boolean equations for combinational behavior – List states, and transitions among states • Example: Make x change toggle (0 to 1, or 1 to 0) every clock cycle • Two states: “Off” (x=0), and “On” (x=1) • Transition from Off to On, or On to Off, on rising clock edge • Arrow with no starting state points to initial state (when circuit first starts) Outputs: x OnOff x=0 x=1 clk̂ clk̂ Off On Off On Off On Off On cycle 1 Off OffOn On cycle 2 cycle 3 cycle 4 clk state x Outputs: 26 Digital Design Copyright © 2006 Frank Vahid FSM Example: 0,1,1,1,repeat • Want 0, 1, 1, 1, 0, 1, 1, 1, ... – Each value for one clock cycle • Can describe as FSM – Four states – Transition on rising clock edge to next state Off OffOn1On1 On2 On2On3 On3Off clk x State Outputs: Outputs: x On1Off On2 On3 clk^ clk^ clk^x=1x=1x=0 x=1clk^ 27 Digital Design Copyright © 2006 Frank Vahid Extend FSM to Three-Cycles High Laser Timer • Four states • Wait in “Off” state while b is 0 (b’) • When b is 1 (and rising clock edge), transition to On1 – Sets x=1 – On next two clock edges, transition to On2, then On3, which also set x=1 • So x=1 for three cycles after button pressed Off OffOn1Off Off Off On2 On3Off clk State Outputs: Inputs: x b On2On1 On3 Off clk^ clk^ x=1x=1x=1 x=0 clk^ b’*clk̂ b*clk^ Inputs: b; Outputs: x 28 Digital Design Copyright © 2006 Frank Vahid FSM Simplification: Rising Clock Edges Implicit • Showing rising clock on every transition: cluttered – Make implicit -- assume every edge has rising clock, even if not shown – What if we wanted a transition without a rising edge • We don’t consider such asynchronous FSMs -- less common, and advanced topic • Only consider synchronous FSMs -- rising edge on every transition Note: Transition with no associated condition thus transistions to next state on next clock cycle On2On1 On3 Off x=1x=1x=1 x=0 b’ b Inputs: b; Outputs: x On2On1 On3 Off x=1x=1x=1 x=0 b’ clk^ clk^ ^clk *clk̂ *clk^b Inputs: b; Outputs: x a 37 Digital Design Copyright © 2006 Frank Vahid Controller Design: Laser Timer Example (cont) • Step 4: Create state table x=1 x=1 x=1 x=0 b b’ 01 00 10 11On2On1 Off On3 Inputs: b; Outputs: x Combinational logic State register s1 s0 n1 n0 xb clk FS M in pu ts FSM outputs a 38 Digital Design Copyright © 2006 Frank Vahid Controller Design: Laser Timer Example (cont) • Step 5: Implement combinational logic Combinationallogic State register s1 s0 n1 n0 xb clk FS M in pu ts FSM outputs a x = s1 + s0 (note from the table that x=1 if s1 = 1 or s0 = 1) n1 = s1’s0b’ + s1’s0b + s1s0’b’ + s1s0’b n1 = s1’s0 + s1s0’ n0 = s1’s0’b + s1s0’b’ + s1s0’b n0 = s1’s0’b + s1s0’ 39 Digital Design Copyright © 2006 Frank Vahid Controller Design: Laser Timer Example (cont) • Step 5: Implement combinational logic (cont) a x = s1 + s0 n1 = s1’s0 + s1s0’ n0 = s1’s0’b + s1s0’ Combinational logic State register s1 s0 n1 n0 xb clk FS M in pu ts FSM outputs n1 n0 s0s1 clk Combinational Logic State register b FSM outps FSM inputs x 40 Digital Design Copyright © 2006 Frank Vahid Understanding the Controller’s Behavior s0s1 b x n1 n0 x=1 x=1 x=1 b 01 10 11On2On1 Off On3 00 0 0 0 0 0 0 b’ 0 0 0 00 x=0 00 0 clk clk Inputs: Outputs: 1 0 10 b 1 0 1 0 0 s0s1 b x n1 n0 x=1 x=1 x=1 b’ 01 10 11On2On1 Off On3 clk b x 00 0 0 x=0 00 0 state=00 state=00 s0s1 b x n1 n0 x=1 x=1 x=1 x=0 b b’ 01 00 10 11On2On1 Off On3 1 0 1 1 0 0 0 1 1 0 clk 0 1 01 state=01 a 41 Digital Design Copyright © 2006 Frank Vahid Example: Seq. Circuit to FSM (Reverse Engineering) clk State register y z FSM outps FSM inputs n0 n1 s0s1 x What does this circuit do? Work backwards y=s1’ z = s1s0’ n1=(s1 xor s0)x n0=(s1’*s0’)x a Pick any state names you want A D B C states Outputs:y, z A D B yz=01yz=00 yz=10yz=10 C states with outputs A D B yz=00 yz=01 yz=10 yz=10 C Inputs: x; Outputs:y, z x’ x’ x’ x x x states with outputs and transitions 42 Digital Design Copyright © 2006 Frank Vahid Controller Example: Sequence Generator • Want generate sequence 0001, 0011, 1100, 1000, (repeat) – Each value for one clock cycle – Common, e.g., to create pattern in 4 lights, or control magnets of a “stepper motor” 00 01 10 11A B D wxyz=0001 wxyz=1000 wxyz=0011 wxyz=1100 C Inputs: none; Outputs: w,x,y,z Step 3: Encode states Step 4: Create state table clk State register w x y z FSM outps n0s0s1 n1 Step 5: Create combinational circuit w = s1 x = s1s0’ y = s1’s0 z = s1’ n1 = s1 xor s0 n0 = s0’ a Step 1: Create FSM A B D wxyz=0001 wxyz=1000 wxyz=0011 wxyz=1100 C Inputs: none; Outputs: w,x,y,z Step 2: Create architecture Combinational logic n0 s1 s0 n1 clk State register w x y z 43 Digital Design Copyright © 2006 Frank Vahid Controller Example: Secure Car Key • (from earlier example) K1 K2 K3 K4 r=1 r=1 r=0 r=1 Wait r=0 Inputs: a; Outputs: r a’a S te p 1 FSM Combinational logic s2 s1 s0 n2 ra n1 n0 clk State register FSM inputs outps S te p 2 a’ a r=0 r=1 r=1 r=0 r=1 000 001 010 011 100 Inputs: a; Outputs: r S te p 3 Step 4 a We’ll omit Step 5 44 Digital Design Copyright © 2006 Frank Vahid Controller Example: Button Press Synchronizer • Want simple sequential circuit that converts button press to single cycle duration, regardless of length of time that button actually pressed – We assumed such an ideal button press signal in earlier example, like the button in the laser timer controller cycle1 cycle2 cycle3 cycle4clk Inputs: Outputs: bi bo Button press synchronizer controller bi bo 45 Digital Design Copyright © 2006 Frank Vahid Controller Example: Button Press Synchronizer (cont) A B C s1 0 0 0 0 1 1 1 1 s0 0 0 1 1 0 0 1 1 bi 0 1 0 1 0 1 0 1 Inputs n1 0 0 0 1 0 1 0 0 n0 0 1 0 0 0 0 0 0 bo 0 0 1 1 0 0 0 0 Outputs Combinational logic unused Step 4: State table a Step 1: FSM A B C bo=1bo=0 bo=0 bi bibi’ bi’ bi’ bi FSM inputs: bi; FSM outputs: bo Step 3: Encode states 00 01 10 bo=1bo=0 bo=0 bi bi bi’ bi’ bi’ bi FSM inputs: bi; FSM outputs: bo Step 5: Create combinational circuit FSM Step 5: Create combinational circuit clk State register outps bo bi s1 s0 n1 n0 Combinational logic n1 = s1’s0bi + s1s0bi n0 = s1’s0’bi bo = s1’s0bi’ + s1’s0bi = s1s0 Step 2: Create architecture Combinational logic n0 s1 s0 n1 bobi clk State register FS M in pu ts FS M ou tp ut s 46 Digital Design Copyright © 2006 Frank Vahid Common Pitfalls Regarding Transition Properties • Only one condition should be true – For all transitions leaving a state – Else, which one? • One condition must be true – For all transitions leaving a state – Else, where go? a b ab=11 – next state? a a’b a what if ab=00? a a’b a’b’ a’b a 47 Digital Design Copyright © 2006 Frank Vahid Verifying Correct Transition Properties • Can verify using Boolean algebra – Only one condition true: AND of each condition pair (for transitions leaving a state) should equal 0 proves pair can never simultaneously be true – One condition true: OR of all conditions of transitions leaving a state) should equal 1 proves at least one condition must be true – Example a a’b a + a’b = a*(1+b) + a’b = a + ab + a’b = a + (a+a’)b = a + b Fails! Might not be 1 (i.e., a=0, b=0) a Q: For shown transitions, prove whether: * Only one condition true (AND of each pair is always 0) * One condition true (OR of all transitions is always 1) a * a’b = (a * a’) * b = 0 * b = 0 OK! Answer: 48 Digital Design Copyright © 2006 Frank Vahid Evidence that Pitfall is Common • Recall code detector FSM – We “fixed” a problem with the transition conditions – Do the transitions obey the two required transition properties? • Consider transitions of state Start, and the “only one true” property Wait Start Red1 Red2GreenBlue s’ a’ a’ ab ag ar a’ a’u=0 u=0 ar u=0 s u=0 u=0 u=1 a ar * a’ a’ * a(r’+b+g) ar * a(r’+b+g) = (a*a’)r = 0*r = (a’*a)*(r’+b+g) = 0*(r’+b+g) = (a*a)*r*(r’+b+g) = a*r*(r’+b+g) = 0 = 0 = arr’+arb+arg = 0 + arb+arg = arb + arg = ar(b+g) Fails! Means that two of Start’s transitions could be true Intuitively: press red and blue buttons at same time: conditions ar, and a(r’+b+g) will both be true. Which one should be taken? Q: How to solve? a A: ar should be arb’g’ (likewise for ab, ag, ar) Note: As evidence the pitfall is common, we admit the mistake was not intentional. A reviewer of the book caught it.