Understanding Flip-Flops in Sequential Logic: SR Latches, D Latches, and Flip-Flops, Study notes of Computer Science

Download Understanding Flip-Flops in Sequential Logic: SR Latches, D Latches, and Flip-Flops and more Study notes Computer Science in PDF only on Docsity! Section 6.1 − Sequential Logic – Flip-Flops Page 1 of 5 6. Sequential Logic – Flip-Flops Combinatorial components: their output values are computed entirely from their present input values. Sequential components: their output values are computed using both the present and past input values. In other words, their outputs depend on the sequence of input values that have occurred over a period of time. This dependence on the past input values requires the presence of memory elements. The values stored in memory elements define the state of a sequential component. Since memory is finite, therefore, the sequence size must always be finite, which means that the sequential logic can contain only a finite number of states. So sequential circuits are sometimes called finite-state machines. Sequential circuits can be a asynchronous or synchronous. Asynchronous sequential circuits change their state and output values whenever a change in input values occurs. Synchronous sequential circuits change their states and output values at fixed points of time, which are specified by the rising or falling edge of a free-running clock signal. Clock period is the time between successive transitions in the same direction, i.e., between two rising or two falling edges. Clock frequency = 1/clock period Clock width is the time during which the value of the clock signal is equal to 1. Duty cycle is the ratio of clock width and clock period. Active high if the state changes occur at the clock's rising edge or during the clock width. Active low if the state changes occur at the clock's falling edge. Latches and flip flops are the basic storage elements that can store one bit of information. 6.1 SR Latch The simplest memory element. Consists of two cross-coupled NOR gates. Inputs S (set) and R (reset) are normally 0. Both active high. Asserting S (setting S=1) will make output Q=1. Asserting R (setting R=1) will make Q=0. t1t0 t2 t3 t4 t5 t6 t7 t8 t9 t10 1 .4 1 .4 1 .4 1 .4 1 .4 1 .4 1 .41 .42 .8 2 .8 2 .8 S R Q Q' One problem inherent in the SR latch is the fact that if both S and R are disasserted at the same time, we cannot predict the latch output (as in t10). The SR latch can also be implemented with NAND gates. S and R are normally 1. They are active low. Clock wid th Ris ing edge Fa l l ing edge Clock pe r iod Q' Q S R 1 0 0 1 Q Q' S R S R Q Qnext Q'next 0 0 0 0 1 0 0 1 1 0 0 1 x 0 1 1 0 x 1 0 1 1 x 0 0 nand 0 1 0 1 1 1 1 0 nor 0 1 0 1 0 1 0 0 S R Q Qnext Q'next 1 1 1 1 0 1 1 0 0 1 1 0 x 0 1 0 1 x 1 0 0 0 x 1 1 Section 6.1 − Sequential Logic – Flip-Flops Page 2 of 5 6.2SR Latch with Enable Similar to the SR latch but with the extra control input C which enables or disables the operation of the S and R inputs. When C=1, the gated SR latch operates as an SR latch. When C=0, S and R are disabled and the circuit persists in the preceding state. 6.3 Gated D Latch D latch ensures that inputs S and R never equal to 1 at the same time. Also SR latches are useful in control applications where we often think in terms of setting or resetting a flag to some condition. However, we often need latches to store bits of information and a D latch may be used in such an application. Gated D latch is constructed from a gated SR latch with an inverter added between the S and the R inputs and use a single D (data) input. The C (control) input is active high in this design but can also be active low. When the C input is asserted, the Q output follows the D input. In this situation, the latch is said to be “open” and the path from D input to Q output is “transparent”; the circuit is often called a transparent latch for this reason. When the C input is negated, the latch “closes”; the Q output retains its last value and no longer changes in response to D. Latches are often called level-sensitive latches because they are enabled and transparent whenever C is asserted. Method 2: Gated D latch can also be implemented using a multiplexer. nega t ive l a t ch D p a s s e s t o Q w h e n C = 0 0 1 s yD Q C pos i t ive l a tch D p a s s e s t o Q w h e n C = 1 0 1 s y D Q C 4 .0 2 .0 C D Q 4.0 3 .0 tse tup t hold Delay through one AOI ga tes i s 2 .0 Problem with the D latch: there is a (shaded) window of time around the falling edge of C when the D input must not change. This window begins at time tsetup before the falling (latching) edge of C; tsetup is called the setup time. The window ends at time thold afterward; thold is called the hold time. 2 2 Q' Q S R C 2 2 Q Q' D C 1 1 1 0 Q Q' D C C S R Q Qnext 0 x x 0 0 0 x x 1 1 1 0 0 0 0 1 0 0 1 1 1 0 1 x 0 1 1 0 x 1 1 1 1 x NA C D Q Qnext 0 x 0 0 0 x 1 1 1 0 x 0 1 1 x 1 nor 0 1 0 1 0 1 0 0