Understanding Sequential Logic: Latches, Flip-Flops, and Timing - Prof. Andrew Fagg, Assignments of Aerospace Engineering

Download Understanding Sequential Logic: Latches, Flip-Flops, and Timing - Prof. Andrew Fagg and more Assignments Aerospace Engineering in PDF only on Docsity! Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 1 Today Sequential logic • Latches • Flip-flops • Counters Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 2 Time Until now: we have essentially ignored the issue of time • We have assumed that our digital logic circuits perform their computations instantaneously • Our digital logic circuits have been “stateless” – Once you present a new input, they forget everything about previous inputs Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 5 Timing Notation time X Either high or low (but well defined and constant) low In transition (undetermined) Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 6 NAND Latch What does this circuit do? Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 7 NAND Latch Consider this initial state Is this a stable state? 1 0 1 1 Yes! Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 10 NAND Latch Now S is set 1 – what happens? 1 1->? 1 0->? Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 11 NAND Latch Q and Q’ remain the same! 1 1->1 1 0->1 So Q and Q’ retain a memory of past state! Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 12 NAND Latch Now set R to 0 – what happens? 1 1->? 0 0->? Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 15 NAND Latch Finally: set R to 1 – what happens? Q and Q’ do not change state 1 0->0 1 1->1 Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 16 Timing Diagram Representation S R Q Q’ ? Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 17 Timing Diagram Representation S R Q Q’ Note small delay in response in Q and Q’ Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 20 Timing Diagram Representation S R Q Q’ Q and Q’ flip state Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 21 Timing Diagram Representation S R Q Q’ How about this case? Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 22 Timing Diagram Representation S R Q Q’ No change in Q and Q’ Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 25 Flip Flops • Add one more input to the circuit: a “clock” signal • We will only allow the state of the output to change in response to S & R when the clock transitions from 1 to 0 Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 26 Flip Flops • Add one more input to the circuit: a “clock” signal • We will only allow the state of the output to change in response to S & R when the clock transitions from 1 to 0 Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 27 Flip Flops Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 30 R-S Flip Flop Clock goes low again 0 0 1->0 0 1 1 1 0->1 1 1->0 0 1 Still no change in Q and Q’ Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 31 R-S Flip Flop S goes high 0->1 0 0 0 1 1 1 1 1 0 0 1 Nothing in the circuit changes Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 32 R-S Flip Flop Now: clock goes high 1 0 0->1 0->1 1->0 1->0 1 1->0 1 0->1 0 1 The state of the first latch changes Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 35 R-S Flip Flop The timing of the drop of S is not critical • But it must do so before the clock goes low Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 36 R-S Flip Flop Timing Diagram Representation S R Q Q’ C The circuit will require a specified amount of “setup time” Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 37 R-S Flip Flop Summary Behaves like an R-S latch – but: • The flip flop will only “pay attention” to the R-S inputs on the falling edge of the clock Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 40 Today Sequential circuits continued • Clocked R-S latch • D Flip flop • Binary coding • Shift registers • Counters Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 41 Administrivia • Mark back? • Homework 1 is out: – Due Feb 17th @ 5:00 • Project 1: – Worth 8% of your final grade – The group that demonstrates successfully first will receive an extra 0.5% of extra credit Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 42 Latch vs Flip flop • Latch implements a simple form of memory • A flip flop adds: – Precise control over when the state of the memory changes Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 45 Clocked R-S Latch S R Q Q’ C Q and Q’ flip state when the clock is high Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 46 Clocked R-S Latch How is this different than our R-S flip flop? Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 47 Clocked R-S Latch S R Q Q’ C What do Q and Q’ do? Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 50 Clocked R-S Latch S R Q Q’ C S triggers set Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 51 Clocked R-S Latch S R Q Q’ C Clock goes low: No further changes in state Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 52 R-S Latch vs Flip Flop What would the R-S flip flop do? Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 55 R-S Flip Flop State change happens at a very precise time Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 56 R-S Flip Flop State change happens at a very precise time But: • We must guarantee that R and S are never high at the same time • We would like to be able to store the high/low state of a single line Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 57 D-Type Flip Flop Replace R/S with D • In essence, R is replaced with D’ Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 60 D-Type Flip Flop Clock transitions from high to low 1->0 1 1 0->1 0 1 0->1 1->0 1 Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 61 D-Type Flip Flop Clock transition -> ‘set’ of the slave latch 1->0 1 1 0->1 0 1 0->1 1->0 1 1 0 Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 62 D-Type Flip Flop D=0 results in a ‘reset’ of the latch 1 0 0 1 Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 65 D Flip Flop D Q Q’ C What happens to Q and Q’? Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 66 D Flip Flop D Q Q’ C What happens to Q and Q’? Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 67 D Flip Flop D Q Q’ C What happens to Q and Q’? Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 70 An Application of D Flip Flops What does this circuit do? Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 71 Shift Register On each clock transition from high to low: • X0 takes on the current value of D • X1 <- X0 • X2 <- X1 Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 72 Another D Flip Flop Circuit How does this circuit behave? Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 75 A Bit About Binary Encoding If a boolean variable can only encode two different values, how do we represent a larger number of values? www.thinkgeek.com Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 76 Binary Encoding How do we represent a larger number of values? • As with our decimal number system: we concatenate binary digits (or “bits”) into strings Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 77 Binary Encoding • The first (rightmost) bit is the 1’s digit • The second bit is the 2’s digit • The ith bit is the 2i-1 ’s digit Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 80 Today • A little more on number systems • Arithmetic operators • Representing negative numbers • Multiplication with shift registers • Arithmetic logic units Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 81 Administrivia • Homework 1 due in 1 week • Project 1: – One robot is now up and stable – A complete set of power supplies will be available today Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 82 Binary to Decimal Conversion K++++= 3322110 2*2*2* BBBBvalue ∑ − = = 1 0 2* N i i iBvalue How do we convert from decimal to binary? Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 85 Binary Counter How would we build a circuit that counts the number of clock ticks that have gone by? Insight: • B1 changes state at half the frequency that B0 does • B2 changes state at half the frequency of B1 111 011 101 001 110 010 100 000 B0B1B2 Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 86 Ripple Counter The carry “ripples” down the chain … Andrew H. Fagg: Embedded Real-Time Systems: Sequential Logic 87 J-K Flip Flops Behave similarly to R-S flip flops, but: • Deal properly with the case where both R and S inputs are 1 – The R-S flip flop will arbitrarily choose one of the possible output states • The master latch (on the input side) can only change state once while the clock is high