Understanding Sequential Circuits: Fundamental Mode vs. Pulse Mode and Flip-Flops, Slides of Computer Science

Download Understanding Sequential Circuits: Fundamental Mode vs. Pulse Mode and Flip-Flops and more Slides Computer Science in PDF only on Docsity! Sequential Networks Two major classes of Sequential Circuits 1. Fundamental Mode – A sequential circuit where: • Only one input is allowed to change at any given time • no input change is permitted until internal changes caused by previous input transition have completed. (stable input transition property) Example: latches and flip-flops 2. Pulse Mode – A sequential circuit that responds only to pulses Example: clocked synchronous systems Docsity.com Model of Sequential Networks Combinational Logic Circuit Memory Elements - flip-flop - latch - register - PROM n m s s s-bit Present State Variables, Y s-bit Next State Excitation Variables Ei (X,Y) Input Variables, X Output Variable, Z yi (t+∆ti) xi (t) yi (t) Docsity.com Clock Signal Example What is the pulse-width of a 4.77 MHz clock with a 30% duty cycle? τ = 1/f = (4.77×106)-1 = 2.096 ×10-7 = 210 ns Pw = (duty cycle) × τ = (0.3) × (210 ns) = 63 ns What about clock rise- and fall-time? Clocks are normally defined as having maximum rise and fall times (e.g., time between 10% and 90% values) or they are implied through pulse width specifications. Docsity.com Common Memory Element - Flip-Flops S R Q Q Q Q J K Q Q D Q Q T Behavior is Described by Characteristic Table or Equation Most Commonly Encountered Device is the D-flip-flop S R Q(t+1) 0 0 Q(t) 0 1 0 1 0 1 1 1 undef J K Q(t+1) 0 0 Q(t) 0 1 0 1 0 1 1 1 Q'(t) D Q(t+1) 0 0 1 1 T Q(t+1) 0 Q(t) 1 Q'(t) ( 1) ( )Q t S RQ t+ = + ( 1) ( ) ( )Q t JQ t KQ t+ = + ( 1)Q t D+ = ( 1) ( ) ( )Q t TQ t TQ t+ = + Docsity.com Concept of State • The Q Outputs of the Flip-Flops Form a State Vector • A Particular Set of Outputs is the Present State • The Particular State Vector that will Occur at the Next Discrete Time is the Next State • A Sequential Circuit described in Terms of State is a Finite State Machine (FSM) Docsity.com Representing/Describing FSMs Present State Next State Output x=0 x=1 x=0 x=1 A(t)B(t) A(t+1)B(t+1) A(t+1)B(t+1) y(t) y(t) 00 00 01 0 0 01 00 11 1 0 10 00 10 1 0 11 00 10 1 0 State Table Timing Diagram CLK A B x y Note: propagation delays and change in y before clock edge Docsity.com FSM Design • Specification Given as One of Previous Descriptions – State Table – State Equations – State Diagram (Easiest to Generate Initially) – ASM Chart (Preferred) • Designer’s Job is to Generate Schematic • Instead of Characteristics, we are Given Excitations • Individual flip-flops have Specific Excitations Docsity.com Flip-Flop Excitations S R Q Q Q Q J K Q Q D Q Q T Input Behavior is Described by Excitation Table or Equation Most Commonly Encountered Device is the D-flip-flop Q(t) Q(t+1) S R 0 0 0 X 0 1 1 0 1 0 0 1 1 1 X 0 Q(t) Q(t+1) D 0 0 0 0 1 1 1 0 0 1 1 1 Q(t) Q(t+1) J K 0 0 0 X 0 1 1 X 1 0 X 1 1 1 X 0 Q(t) Q(t+1) T 0 0 0 0 1 1 1 0 1 1 1 0 Docsity.com Vending Machine Example State Diagram and State Table Q0, initial state without money Q2, machine received a half-dollar Q1, machine received a quarter Docsity.com Vending Machine Example State Assignment and Transition Table Table 6.7 State assignment. Table 6.8 Transition table. Internal state | yi 2 Qo 0 0 Qi 0 1 Qo 1 0O £122 Y1Yy2 00 01 10 00 | 00, 00 | 01, 00 | 10, 00 01 | 01, 00 | 10, 00 | 00, 10 10 | 10, 00 | 00, 10 | 00, 11 Docsity.com Vending Machine Example SR Implementation with Separate Maps L djalx x 1 d d 2 2 X IX [XIX x y x qd x 1 1 x2 %2 (a) S) (b) R; x x 1 d XI} d x 1 1 2 2 x|X| xX] x x y y x d}/d|xX]a 71 % (c). S2 (d) Rz Figure 6.12 Map showing the inputs for SR-FF. RiDig ah ea , tD- IR, Y;p}+ 2 Rp Ya} 2 Feiss AAS a Be Figure 6.13 Excitation networks for $R-FF. ® Docsity.com