Download Understanding Memory Devices: Capacitive Loads, SR Latches, and Flip-Flops and more Slides Digital Systems Design in PDF only on Docsity! Sequential Networks Docsity.com Part II. Sequential Networks (Ch. 3) Memory / Timesteps Clock Memory: Flip flops Specification: Finite State Machines Implementation: Excitation Tables xi yi si yi=fi(S t,X) si t+1=gi(S t,X) Docsity.com Capacitive Loads Q Q I1 I2 0 1 1 0 โข Consider the two possible cases: โ Q = 0: then Qโ = 1 and Q = 0 (consistent) โ Q = 1: then Qโ = 0 and Q = 1 (consistent) โ Bistable circuit stores 1 bit of state in the state variable, Q (or Qโ ) โข But there are no inputs to control the state Q Q I1 I2 1 0 0 1 Docsity.com SR (Set/Reset) Latch R S Q Q N1 N2 โข SR Latch โข Consider the four possible cases: โ S = 1, R = 0 โ S = 0, R = 1 โ S = 0, R = 0 โ S = 1, R = 1 Docsity.com SR Latch Analysis โ S = 1, R = 0: then Q = 1 and Q = 0 โ S = 0, R = 1: then Q = 0 and Q = 1 R S Q Q N1 N2 0 1 R S Q Q N1 N2 1 0 Docsity.com S R y Q Q = (R+y)โ y = (S+Q)โ Docsity.com Flip-flop Components S R SR F-F (Set-Reset) Inputs: S, R State: (Q, y) y Q Docsity.com Id Q y S R y* Q* y** Q** y*** Q*** 0 0 0 0 0 1 1 0 0 1 1 1 0 0 0 1 1 0 1 0 1 0 2 0 0 1 0 0 1 0 1 0 1 3 0 0 1 1 0 0 0 0 0 0 4 0 1 0 0 1 0 1 0 1 0 5 0 1 0 1 1 0 1 0 1 0 6 0 1 1 0 0 0 0 1 0 1 7 0 1 1 1 0 0 0 0 0 0 8 1 0 0 0 0 1 0 1 0 1 9 1 0 0 1 0 0 1 0 1 0 10 1 0 1 0 0 1 0 1 0 1 11 1 0 1 1 0 0 0 0 0 0 12 1 1 0 0 0 0 1 1 0 0 13 1 1 0 1 0 0 1 0 1 0 14 1 1 1 0 0 0 0 1 0 1 15 1 1 1 1 0 0 0 0 0 0 Q y State Transition SR 10 1 00 11 00 10 SR 11 10 01 11 01 11 01 10 00 10 00 01 00 11 State Diagram 01 Docsity.com SR Latch Symbol โข SR stands for Set/Reset Latch โ Stores one bit of state (Q) โข Control what value is being stored with S, R inputs โ Set: Make the output 1 (S = 1, R = 0, Q = 1) โ Reset: Make the output 0 (S = 0, R = 1, Q = 0) โข Must do something to avoid invalid state (when S = R = 1) S R Q Q SR Latch Symbol Docsity.com D Latch D Latch Symbol CLK D Q Q โข Two inputs: CLK, D โ CLK: controls when the output changes โ D (the data input): controls what the output changes to โข Function โ When CLK = 1, D passes through to Q (the latch is transparent) โ When CLK = 0, Q holds its previous value (the latch is opaque) โข Avoids invalid case when Q โ NOT Q Docsity.com D Latch Internal Circuit S R Q Q Q Q D CLK D R S CLK D Q Q S R Q QCLK D 0 X 1 0 1 1 D Docsity.com D Flip-Flop vs. D Latch CLK D Q Q D Q Q CLK D Q (latch) Q (flop) Docsity.com D Flip-Flop vs. D Latch CLK D Q Q D Q Q CLK D Q (latch) Q (flop) Docsity.com Latch and Flip-flops (two latches) Latch can be considered as a door CLK = 0, door is shut CLK = 1, door is unlocked A flip-flop is a two door entrance CLK = 1 CLK = 0 CLK = 1 Docsity.com D Flip-Flop (Delay) D CLK Q Qโ Id D Q(t) Q(t+1) 0 0 0 1 1 0 1 0 2 1 0 1 3 1 1 - Characteristic Expression Q(t+1) = D(t) 0 0 1 1 0 1 PS D 0 1 State table NS= Q(t+1) Docsity.com JK F-F J CLK Q Qโ 0 0 0 1 ? 1 1 0 1 ? PS JK 00 01 10 11 State table Q(t+1) K Docsity.com JK F-F J CLK Q Qโ Characteristic Expression Q(t+1) = Q(t)Kโ(t)+Qโ(t)J(t) 0 0 0 1 1 1 1 0 1 0 PS JK 00 01 10 11 State table Q(t+1) K Docsity.com
