Shift Register - Computer Science - Lecture Slides, Slides of Computer Science

Download Shift Register - Computer Science - Lecture Slides and more Slides Computer Science in PDF only on Docsity! 4-bit Shift Register SERIAL | | | —p) 0 D Q D ) D Q CLR ® Docsity.com 2-bit Register Hing, buffer t Q Le 1 Da Data P. Q input oo Kt i o data output ral load logic control signals Daj Db aL) [ce te ll dr | dr —Tunre | hi | 7 a ear 4 1 os Two two-bit registers connected to.a bus with three-state buffers Docsity.com Synchronous Counter Synchronous counter Clock in +5 Jog | —|J ct K Li kK CLR CLR Docsity.com —(Clear Ring Counter an 0) | CLR CLR Cloek in Docsity.com Up/down counter library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; -- up/down counter entity counterupdown is port (load,reset, clk : in std_logic; -- control signal dir : in std_logic; -- direction d : in std_logic_vector (3 downto 0); q : out std_logic_vector (3 downto 0) ); end counterupdown; Docsity.com Binary counter library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity binarycounter is port (clk : in std_logic; q : out std_logic_vector (3 downto 0) ); end binarycounter; Docsity.com architecture behave of binarycounter is signal temp : std_logic_vector (3 downto 0); begin a: process (clk) begin if (clk'event and clk = '0') then temp <= temp + "0001"; end if; q <= temp; end process a; end behave; Docsity.com Waveform (binary counter) i x tue estan eenae ea eae Help x pean rue ne tues Edit View Node As: A?) >| BS BSD) | Le) a) ?96.Ons | ae a as) gi A Gre S| cee Sige MAX-+plus IT Ci) ce a) 0.Ons [els] Time: [796.0ns Interval: Ts | Ref A o.Ons 3e|| tame Walue. t 100.0ns 200.0ns 300,.0ns 400.0ns 500,0ns 600.0ns 700.0ns 800,0ns 900.0ns 1.0 a clk a | l l | | ae 4 ba o 1 2 a 4 _—_| a temp B oo00 Oooo oo0t oo10 0071 o1o00 @)) ay 22\dataa[3..0]| B oO00 Oooo oo0t oo10 0071 o1o00 = ay derldataa[S..0]] 6 OOOO Oooo oo0t oo10 0071 o1o0 Cell < Docsity.com