Sizing Chains of Inverters and Extracting Wire Capacitances in VLSI Systems Design - Prof., Study notes of Electrical and Electronics Engineering

Download Sizing Chains of Inverters and Extracting Wire Capacitances in VLSI Systems Design - Prof. and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! Slide 1W. Rhett Davis NC State University ECE 546 Fall 2008 ECE 546 - VLSI Systems Design Lecture 6: Sizing for Large Loads, Wire Extraction & Delay Fall 2008 W. Rhett Davis NC State University with significant material from Rabaey, Chandrakasan, and Nikolić Slide 2W. Rhett Davis NC State University ECE 546 Fall 2008 Announcements HW#2 Due Tuesday, Sept. 9 HW#3 Due Tuesday, Sept. 16 Slide 3W. Rhett Davis NC State University ECE 546 Fall 2008 Summary of Last Lecture What are the different components of the effective load capacitance (CL) for an inverter loaded with an identical inverter? What is the best way to choose the ratio β = Wp/Wn for an Inverter? Slide 4W. Rhett Davis NC State University ECE 546 Fall 2008 Today’s Lecture Driving Large Capacitances (5.4.3) Extracting Wire Capacitances (4.1 – 4.3.2) » Classical (inter-layer area + fringe) » Modern (intra-layer coupling) » Cross-Talk Delay Noise Slide 5W. Rhett Davis NC State University ECE 546 Fall 2008 Inverter Chain CL If CL is given: - How many stages are needed to minimize the delay? - How to size the inverters? May need some additional constraints. In Out Slide 6W. Rhett Davis NC State University ECE 546 Fall 2008 Inverter Delay • Unit Inverter • Minimum length devices, L=50 nm • WN=Wunit, WP = const*Wunit (e.g. const=2) • same pull-up and pull-down currents • approx. equal resistances RN = RP = Runit • output capacitance Cunit • approx. equal rise tpLH and fall tpHL delays • Larger Inverters • s = size • WN=s*Wunit, WP= s*const*Wunit • RN = RP = RS = Runit(Wunit/WN) = Runit/s • output (internal) capacitance Cint = Cunit(WN/Wunit) = Cunit*s • Delay = tp = 0.69 RS (Cint+CL) 2W W Slide 7W. Rhett Davis NC State University ECE 546 Fall 2008 Inverter with Load Load Delay Cint CL Delay = 0.69 RS (Cint + CL) = 0.69 RSCint + 0.69 RS CL = 0.69 RS Cint (1+ CL /Cint) = Delay (Internal) + Delay (Load) 2W W Slide 8W. Rhett Davis NC State University ECE 546 Fall 2008 Delay Formula ( ) ( ) ( )γ/1/169.0 ~ 0int ftCCCRt CCRDelay pintLSp LintS +=+= + Cint = γCin with γ ≈ 1 (1.1 in our process) f = CL/Cin - effective fanout RS = Runit/s Cint = Cunit*s tp0 = 0.69RunitCunit Slide 17W. Rhett Davis NC State University ECE 546 Fall 2008 Summary of Sizing Optimum fan-out » fopt satisfies » (plug in different values for f in this equation until it is satisfied) » Sizing a chain of inverters » single stage delay – γ = Cint/Cin ≈ 0.75 – f = CL/Cin for stage » multi-stage delay – N = no. of stages – F = CL / Cin for chain – ( )γ/10 Npp FNtt += N Ff = ( )ff γ+= 1exp opt opt f FN ln ln = ( )γ/10 ftt pp += Slide 18W. Rhett Davis NC State University ECE 546 Fall 2008 Today’s Lecture Driving Large Capacitances (5.4.3) Extracting Wire Capacitances (4.1 – 4.3.2) » Classical (inter-layer area + fringe) » Modern (intra-layer coupling) » Cross-Talk Delay Noise Slide 19W. Rhett Davis NC State University ECE 546 Fall 2008 Impact of Interconnect Parasitics Interconnect parasitics » reduce reliability » affect performance and power consumption Classes of parasitics » Capacitive » Resistive » Inductive Slide 20W. Rhett Davis NC State University ECE 546 Fall 2008 The Wire transmitters receivers schematics physical Slide 21W. Rhett Davis NC State University ECE 546 Fall 2008 Wire Models All-inclusive model Capacitance-only Slide 22W. Rhett Davis NC State University ECE 546 Fall 2008 Today’s Lecture Driving Large Capacitances (5.4.3) Extracting Wire Capacitances (4.1 – 4.3.2) » Classical (inter-layer area + fringe) » Modern (intra-layer coupling) » Cross-Talk Delay Noise Slide 23W. Rhett Davis NC State University ECE 546 Fall 2008 Capacitance of Wire Interconnect VDD VDD Vin Vout M1 M2 M3 M4Cdb2 Cdb1 Cgd12 Cw Cg4 Cg3 Vout2 Fanout Interconnect VoutVin CL Simplified Model Slide 24W. Rhett Davis NC State University ECE 546 Fall 2008 Capacitance: The Parallel Plate Model Dielectric Substrate L W H tdi Electrical-field lines Current flow WLcWL t C a di di area == ε Slide 25W. Rhett Davis NC State University ECE 546 Fall 2008 Permittivity For this class, we will assume a porous, low-K dielectric (e.g. Carbon-Doped Silicon Dioxide), with εr = 2.5 Slide 26W. Rhett Davis NC State University ECE 546 Fall 2008 Fringing Capacitance W - H/2H + (a) (b) LcWLc Ht L t WL CC fa di di di di fringearea 2 )/log( 2 += += += πεε totC In general, assume C = Area*ca + Perimeter*cf Slide 27W. Rhett Davis NC State University ECE 546 Fall 2008 Fringing versus Parallel Plate (from [Bakoglu89]) Slide 28W. Rhett Davis NC State University ECE 546 Fall 2008 Wiring Capacitances 473427221817n/a15fringe 3313865483aream6 5734262119n/a23fringe 361486598aream5 52453423n/a41fringe 341397108aream4 463428n/a53fringe 361391313aream3 4938n/a58fringe 34161918aream2 66n/a16fringe 615138aream1 n/afringe 97areapoly m5m4m3m2m1polyactivefield Example values for a 6-metal 180nm process Do not use this approach in this class! Useful for technologies larger that 180nm Units: » area (aF/μm2) » fringe (aF/μm) Slide 37W. Rhett Davis NC State University ECE 546 Fall 2008 Important Notes Total capacitance (sum of all capacitances for one wire) varies by +/- 10% in a layer, depending on adjacency Total capacitance varies +/- 32% across all layers (avg. is 142.5 aF/um). This is why an average capacitance for a wire makes sense in high-level studies, but not for detailed design debugging. Slide 38W. Rhett Davis NC State University ECE 546 Fall 2008 Extracting Capacitances Find the total capacitance of the following wire » 5um, metal 3, nested: Slide 39W. Rhett Davis NC State University ECE 546 Fall 2008 Today’s Lecture Driving Large Capacitances (5.4.3) Extracting Wire Capacitances (4.1 – 4.3.2) » Classical (inter-layer area + fringe) » Modern (intra-layer coupling) » Cross-Talk Delay Noise Slide 40W. Rhett Davis NC State University ECE 546 Fall 2008 Cross-Talk Noise Functional or Glitch Noise Time Aggressor Victim without coupling delay Victim with coupling delayV ol ta ge Delay Noise Slide 41W. Rhett Davis NC State University ECE 546 Fall 2008 Simplified Delay-Noise Model Victim Driver Victim Receiver Ceq ( ) CWeq CCC β−+= 1 assumes victim and aggressor transition at the same time ΔVV is VDD/2 when victim is rising, -VDD/2 when falling ΔVA is the voltage change of the aggressor node while the victim completes the first half of its swing (-2 ≤ β ≤ 2) source: Zhaoran Yan, et al, Intl. Conf. on ASIC 2003 V A V V Δ Δ =β Slide 42W. Rhett Davis NC State University ECE 546 Fall 2008 What is Ceq when... victim aggressor 1) 2) 3) trv tra= trv tra<< trv tfa= trv tra>> 4) Slide 43W. Rhett Davis NC State University ECE 546 Fall 2008 Summary Learned how to size a chain of inverters to drive a large load with minimum delay Learned how to find the optimum number of stages to drive a large load Learned how to extract Cwire in terms of carea, and cfringe Learned how to compute Ceq for a victim wire given CW, CC and the rise/fall time of the victim/aggressor ( )ff γ+= 1exp opt opt f FN ln ln = N Ff =