Crystal Structures: Understanding Atomic Arrangement in Solids - Prof. Aurangzeb Khan, Study notes of Electrical and Electronics Engineering

Download Crystal Structures: Understanding Atomic Arrangement in Solids - Prof. Aurangzeb Khan and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! Transistor Physical Gate Length 1.00 0.5um ° Technology c £ o10 = Transistor 30nn} Physical Gate se, 30nm 001 Length 20pm 4 45nm 1990 1995 2000 2005 2010 Year ‘The physical gate length will reach 15nm before the end of the decade Moore’s Second Law Scaling of Fabrication Facilities Cost 10,000 . - r . r 2x every 4 years 1000 F t cost of a modern water fab (S million) 2x every 3 years ~ 100 F 1970 1980) 1990 1.47x every 2 years 2000 The Chip-Making Process Wrisemorlecian Mask Mfg Materials Mgt., Chemical Dist., Automation, CIM Diffusion? Wafer | DE Photo- Phot wg itocraphy Inpan Inspection & Measurement aaa eee Materials Mgt., CIM, Automation? Wafer Die Wire Encap- Test & BN INFRASTRUCTURE Copyright 1999 1 INFRASTRUCTURE Making the Wafer + The Process: — Aseed crystal is suspended in a molten bath of silicon — It is sSowly pulled up and grows into an ingot of silicon — The ingot is removed and ground down to dameter — The endis cut off, then thin silicon wafers are sawn off (sliced) and polished [BVFRA STRUCTURE Copyright 1999  © The Process — Start witk ul:ra-pure glass plates with a surface deposition of chromium. — Computer generated layouts of the IC drive a lazer beam or electron beam to selectively remove chromium and create thie trresk Or reticle © Design Driven: — increased complexity — long write times — New Produc: Acceleration Tocess ‘Slicon Layout Photomask: eee se Rte The water 1¢ coated with photoresist material # The retiale contzining a feyer's iusage of oue of more die ate exposed hy Hight source thiongh a lers system onto the wafer + The wafer is thea stepped over tothe next die and the provess repeaced unal the wafer is completely exposed [BYFRASTRUCTURE -Copuight 199 5 EE 439/539 Defects kill yield and drive up manufacturing cost, so defect inspection is vital in the Fab. EE 439/539 Crystal structure: How do atoms arrange themselves to form solids? • Fundamental concepts and language • Unit cells • Crystal structures • Face-centered cubic • Body-centered cubic • Hexagonal close-packed • Close packed crystal structures • Types of solids • Single crystal • Polycrystalline • Amorphous Crystal structure: How do atoms arrange themselves to form solids? • Fundamental concepts and language • Unit cells • Crystal structures • Face-centered cubic • Body-centered cubic • Hexagonal close-packed • Close packed crystal structures • Types of solids • Single crystal • Polycrystalline • Amorphous Types of Solids • Crystalline material: atoms self-organize in a periodic array • Single crystal: atoms are in a repeating or periodic array over the entire extent of the material • Polycrystalline material: comprised of many small crystals or grains • Amorphous: lacks a systematic atomic arrangement Crystal Properties of Solid Three types of solids, classified according to atomic arrangement (a) Crystalline (b) Amorphous (c) Polycrystalline Crystal grains of a ceramic material Crystalline materials: The constituent atoms arranged in a pattern that repeats itself periodically in 3-dimensions. EE 439/539 Crystal structure • To discuss crystalline structures it is useful to consider atoms as being hard spheres with well- defined radii. • In this hard-sphere model, the shortest distance between two like atoms is one diameter. • We can also consider crystalline structure as a lattice of points at atom/sphere centers. Unit Cell • The unit cell is the smallest structural unit or building block • that can describe the crystal structure. Repetition of the • unit cell generates the entire crystal. • Example: 2D honeycomb net can • be represented by translation of • two adjacent atoms that form a unit cell for this 2D crystalline structure • Different choices of unit cells possible, generally choose • parallelepiped unit cell with highest level of symmetry Crystals are characterized by a unit cell which repeats in the x, y, z directions. Face-Centered Cubic (FCC) Crystal Structure (I) • Atoms are located at each of the corners and on the centers of all the faces of cubic unit cell • Cu, Al, Ag, Au have this crystal structure Face-Centered Cubic Crystal Structure (II) • The hard spheres or ion cores touch one another across a face diagonal ⇒ the cube edge length, a= 2R√2 • The coordination number, CN = the number of closest neighbors to which an atom is bonded = number of touching atoms, CN = 12 • Number of atoms per unit cell, n = 4. (For an atom that is shared with m adjacent unit cells, we only count a fraction of the atom, 1/m). In FCC unit cell we have: 6 face atoms shared by two cells: 6 x 1/2 = 3 8 corner atoms shared by eight cells: 8 x 1/8 = 1 • Atomic packing factor, APF = fraction of volume occupied by hard spheres = (Sum of atomic volumes)/(Volume of cell) = 0.74 (maximum possible) C60 EE 439/539 Dislocations • Dislocations are line defects. Simplest to visualize is an edge dislocation • – think of an extra half-plane of atoms. • Affects deformation properties – to slide upper block over lower now • only requires a line of bonds to break at a time, not a whole plane – • process of slip. Explains low yield strength of solids. • Sources: i by stress due to temperature gradient ii agglomeration Issues: anti-phase domain boundaries (APBs) 1 µm GaAs Ge APBs reduce reliability/performance •Planar shunt/diffusion paths •surface roughness Zincblende III-V (2 types of atoms) Group IV (1 type of atom) A PB = As = Ga = Ge or Si Electrically active Ga-Ga or As-As bonds APD’s are a potential problem for any III-V/IV heteroepitaxy !!! Crystal Structure Mismatch Silicon Wafer Manufacture Packaging Epitaxial Growth Oxidation Photo- lithography Etching Diffusion (Ion Implantation) Metallization Fabrication Process Flow for VLSI Devices Chip Fabrication Processes Silicon Wafer Preparation EE 439/539 Czochralski (CZ) Growth Method • CZ is more common method to grow silicon crystal today because it is capable of producing large diameter crystals, from which large diameter wafer can be cut. Lecture # 4 Modern CZ Crystal Growth • The raw Si used for crystal growth is purified from SiO2 (sand) through refining, fractional distillation and CVD. • The raw material contains < 1 ppb impurities except for O (» 1018 cm-3) and C (» 1016 cm-3) • Essentially all Si wafers used for ICs today come from Czochralski grown crystals. Polysilicon material is melted, held at close to 1415 °C, and a single crystal seed is used to start the crystal growth. • Pull rate, melt temperature and rotation rate are all important control parameters. Drawback of the CZ method • The only significant drawback to the CZ method is that the silicon is contained in liquid form in a crucible during growth and as a result, impurities from the crucible are incorporated. • in the growing crystal. Oxygen and carbon are the two most significant contaminants. • These impurities are not always a drawback, however. Oxygen in particular can be very useful in mechanically strengthening the silicon crystal and in providing a means for gettering other unwanted impurities during device fabrication. Vpmax= maximum crystal pull rate is inversely proportional to the square root of the crystal radius. EE 439/539 Modeling Dopant Behavior During CZ Crystal Growth • •Dopants are added to the melt to provide a controlled • n or p doping level in the wafers. • However, the dopant incorporation process is complicated by dopant segregation. Ko is the segregation coefficient.CS and CL are the impurity concentration just on the either side of the solid/ liquid interface. f= Vs/Vo, a fraction of melt that has solidified Doping concentration versus position along the grown CZ crystal for common dopants in silicon. Consider three cases: If K<1 If K>1 if K~1 EE 439/539 Future Trends in Technologies • Silicon will be the dominant material used for ICs for as far into the future as we can reliably see. • There will be increasing demand for larger diameter wafers since manufacturing economics favor larger wafers and the resulting larger numbers of chips they can carry. • It is also easy to predict that as device dimensions continue to shrink, in- creasing demands will be made on wafer suppliers to reduce impurity levels in the starting wafers or to tightly control these levels as in the case of oxygen. • The recently introduced MCZ should help in controlling wafer properties. • One of the change that may impact starting wafer in the future is the current interest in Silicon On Insulator (SOI), which result a epitaxial layer. • The advantages of such a structure come about because the devices are built in a thin silicon film on an insulator (SiO2 in this case). This can reduce parasitic capacitances and as a result, speed up circuits. • This process is know as SIMOX for “separation by implanted oxygen” • BESOI for Bonded and etch back technology” Clean Room Clean Room EE 439/539 Typical a person emit 5-10 million particle Per minute. Most modern IC plants Use robots for wafer Handling. H2SO4+H2O2⇒CO2+H2O EE 439/539 Standard RCA cleaning procedure Gettering • Gettering is a favorable mechanism observed in the presence of oxygen at concentration near 1017 cm-3. • When, prior to a device processing a silicon wafer is heated to ~1000oC in N2 atmosphere, most of the oxygen near the surface of the wafer is removed by the atmosphere. Deep in the bulk of crystal , however, oxygen remains at high concentration and precipitates as complexes and acts as a sink that attracts impurities such as heavy metals. • Gettring can be also achieved by intentionally damage the back of the wafer and then subjecting it to high temperature. The damage region act as sink for impurities. • In GaAs replacement of gallium atom with a much larger indium atom creates a strain field that traps the dislocations, effectively gettering them from any active layer grown on top of the wafer. EE 439/539 review Basic lithography process flow- chapter-5 Ten Basic Steps of Photolithography 1. Surface Preparation 2. Photoresist Application 3. Soft Bake 4. Align & Expose* 5. Develop 6. Hard Bake 7. Inspection 8. Etch 9. Resist Strip 10. Final Inspection * Some processes may include a Post-exposure Bake Introduction to the Lithography Process Lithography Overview • While the lithography concept is very simple, the actual implementation is very complex, because of the following demands placed on this process: • Resolution - demand for smaller device structures • Exposure field - chip size and need to expose at least one full chip (8” wafer) • Placement accuracy - alignment with respect to the existing pattern • Throughput - manufacturing cost • Reduction of defects density - yield loss 0.7X in linear dimension every 3 years. • Placement accuracy ≈ 1/3 of feature size. • ≈ 35% of total wafer manufacturing costs for lithography. • Note the ???. This represents the single biggest uncertainty about the future of the roadmap. EE 439/539 Wafer Exposure Systems Contact printing is capable of high resolution but has unacceptable defect densities. Inexpensive, diffraction effects are minimize. • Proximity printing cannot easily print features below a few µm (except for x-ray systems). Poor resolution due to diffraction effects, required 1 X mask. • Projection printing provides high resolution and low defect densities and \ dominates today. • Typical projection systems use reduction optics (2X - 5X), step and repeat or step and scan mechanical systems, print ∼ 50 wafers/hour and cost $5 - 10M. electronic interface computer Stepper E-Beam Lithography Wafer Exposure Systems Photomask • A mask for optical lithography consists of a transparent plate called blank, covered with a patterned film of opaque material. • The blank is made of soda lime, borosilicate glass, or fused quartz. The advantage of the quartz is that it is transparent to deep UV (≤365nm) and has a very low thermal expansion coefficient. EE 439/539 Photolithography • Three ways to improve resolution Wmin (also R is used in the text) • We will derive this expression and analyze all the different means of reducing Wmin(also R) EE 439/539 Photolithography-DOF • The defocus tolerance (DOF) • Much bigger issue in miniaturization science than in ICs A small aperture was used to ensure the foreground stones were as sharp as the ones in the distance. What you need here is a use a telephoto lens at its widest aperture. Photolithography-DOF This depth of focus is on the same order as the resist layer thickness itself. Modulation Transfer Function (MTF) • MTF is a measure of the optical contrast in the aerial image by the exposure system. The higher the MTF the better the optical contrast. MTF of an image can be defined as • MTF increases with decreasing wavelength. • For large features size MTF is unity. As the features size decreases diffraction effects cause the MTF degrade to finally reached zero when the features are so closely spaced that there is no remaining contrast in the image.       + − = minmax minmax II IIMTF Partially dark EE 439/539 Spatial Coherence • A useful definition of the spatial coherence of practical light sources for lithography is simply • S= light source diameter • condensed lens diameter • Practical light sources are not point sources. Therefore, the light striking the mask will not be plane waves. • Typically, S ~ 0.5 to 0.7 in modern systems. Summary of wafer printing systems • In the contact printing system , a very high resolution image is produced i. e., minimum diffraction effect. • In a proximity printing system, the resolution degrade because of near field Fresnel diffraction effects. • In the projection printing system , diffraction effects are minimized by placing a lens between mask and the wafer. And focus the aperture on the wafer. • It is clear from the figure that the resolution of the proximity system is inferior to both of the other systems. This is why projection systems are used in manufacturing today. Discuss implications of following calculation for the technologist that must manufacture transistors with 0.5 µm features. R RExample R Photoresist Composition • The most commonly used positive resist consist of diazonaphtoquinone (DQ), which is the photoactive compound (PAC), and novolac (N), a matrix material called resin. Upon absorption of UV light, the PAC undergoes a structural transformation which is followed by reaction with water to form a base soluble carboxylic acid, which is readily soluble in basic developer (KOH, NAOH, TMAH etc.) The base resin is novolac a long chain polymer consisting of hydrocarbon rings with 2 methyl groups and 1 OH group attached. EE 439/539 Basic Properties of Resists: Contrast Curves • Two basic parameters are used to describe resist properties, contrast and the critical modulation transfer function or CMTF. • Contrast is a measure of the ability of a resist to distinguish between light and dark portion of the mask defined as , )/(log 1 10 of DD =γ The higher the contrast, the sharper the line edge. Resist with high contrast Can actually “sharpen up” a poor aerial image. Example • Find the parameter γ for the • i Positive photoresist Df=90mJ/cm2 and Do=45 mJ/cm2 ii Negative photoresist Df=7mJ/cm2 Do=12mJ/cm2 )/(log 1 10 of DD =γ Critical modulation transfer function (CMTF) • By analogy to the MTF (dark versus light intensities in the arial image produced by the exposure system) defined earlier for optical systems, the CMTF for resists is defined as • In terms of the contrast, can be written as, • In general CMTF < MTF is required for the resist to resolve the aerial image. • •There are often a number of additional issues that arise in exposing resist. 0 0 DD DDCMTF f resist f + − = 110 110 1 1 + − = γ γ resistCMTF EE 439/539 • The third element in the Rayleigh equation is k1. k1 is a complex factor of several variables in the photolithography process such as the quality of the photoresist and the use of resolution enhancement techniques such as phase shift masks, off-axis illumination (OAI) and optical proximity correction (OPC). While exposure wavelengths have been falling and NA rising, k1 has been falling as well, see figure . The practical lower limit for k1 is thought to be about 0.25. Photolithography- k1 • From the discussion to this point, the resolution limit for 193nm exposure systems may be calculated using the Rayleigh equation with, l = 193nm, NA = 0.93 and k1 = 0.25 or • From the above a highly optimized ArF exposure system has an absolute maximum resolution of 52nm, sufficient for 65nm linewidths forecast in 2005, but not capable of meeting the 45nm linewidths forecast in 2007. Photolithography-Immersion Litho • NA is determined by the acceptance angle of the lens and the index of refraction of the medium surrounding the lens. The physical limit for an air based system is clear, but what if a medium with a higher index of refraction is substituted for air? Microscopy has for years used oil between the lens and the sample being viewed for resolution enhancement and it is somewhat surprising that the semiconductor industry has taken this long to seriously consider the merits of replacing air with an alternative. Photolithography-Immersion litho Photolithography-Immersion Litho • The medium between the lens and the wafer being exposed needs to have an index of refraction >1, have low optical absorption at 193nm, be compatible with photoresist and the lens material, be uniform and non-contaminating. Surprisingly, ultrapure water may meet all of these requirements. Water has an index of refraction n = 1.47, absorption of <5% at working distances of up to 6mm, is compatible with photoresist and lens and in it’s ultrapure form is non-contaminating. EE 439/539 Next Generation lithographic methods • Why is optical lithography so widely used and what makes it such a promising method? • It has high throughput, good resolution, low cost and ease in operation. • However, due to deep submicron IC process requirements, optical lithography has limitation that have not yet been solved. • Therefore, it is required to find alternatives to optical lithography. The possible promising techniques are: • Electron beam lithography • Extreme Ultraviolet Lithography • X-ray lithography • Ion beam lithography Schematic of an electron beam lithography machine. Advantages: Generation of submicron Resist geometries Greater depth of focus Direct patterning on a Semiconductor without Using a mask. Currently EBL is the Technology of choice for Mask generation due to Its ability to accurately define small features. Disadvantage: Low throughput Next Generation Lithography: E- Beam oDiffraction is not a limitation on resolution (λ < 1 Å for 10-50 keV electrons) oResolution depends on electron scattering and beam optics the size of the beam, can reach ~ 5 nm oTwo modes of operation: oDirect writing with narrow beam oElectron projection lithography using a mask :EPL oIssues: oThroughput of direct writing is very low : research tool or low pattern density manufacturing oProjection stepper (EPL) is in development stage only (primarily by Nikon). oMask making is the biggest challenge for the projection method oBack-scattering and second electron result in proximity effect –reduce resolution with dense patterns there is also the proximity effect oOperates in high vacuum (10-6 –10-10 torr) –slow and expensive EE 439/539 • The advantages of electron lithography are: (1) Generation of micron and submicron resist geometries (2) Highly automated and precisely controlled operation (3) Greater depth of focus (4) Direct patterning without a mask Next Generation Lithography: E- Beam • The biggest disadvantage of electron lithography is its low throughput (approximately 5 wafers / hour at less than 0.1 µ resolution). Therefore, electron lithography is primarily used in the production of photomasks and in situations that require small number of custom circuits. Issue associated with EBL: Proximity effect • In EBL the resolution is not limited by diffraction • In EBL backscattering causes the electron beam to broaden and expose a large volume of resist then expected. • The proximity effect places a limit on the minimum spacing between pattern feature. SCALPEL® (SCattering with Angular Limitation Projection Electron-beam Lithography) • EPL is e-baem with a mask for high-throughput • The aspect of SCALPEL which differentiates it from previous attempts at projection electron- beam lithography is the mask. This consists of a low atomic number membrane covered with a layer of a high atomic number material: the pattern is delineated in the latter. While the mask is almost completely electron-transparent at the energies used (100 keV), contrast is generated by utilizing the difference in electron scattering characteristics between the membrane and patterned materials. The membrane scatters electrons weakly and to small angles, while the pattern layer scatters them strongly and to high angles. • An aperture in the back-focal (pupil) plane of the projection optics blocks the strongly scattered electrons, forming a high contrast aerial image at the wafer plane • Uses very short 13.4 nm light • All reflective optics (at this wavelength all materials absorb!) • Uses reduction optics (4 X) • Step and scan printing • Optical tricks seen before all apply: off axis illumination (OAI), phase shift masks and OPC • Vacuum operation • Laser plasma source • Very expensive system Next Generation Lithography : EUV EE 439/539 Physical measurements techniques (destructive) • Etching (HF for SiO2 layer), AFM, STM, SEM, TEM (resolution below 10nm). All of these techniques required sample preparation and as a result are not well suited to in process measurements on a manufacturing line. They also provide information on film thickness. SEM image TEM image Example • In an experimental structure in the following figure, a phosphorus N+ region is formed by ion implantation using a 50-nm Sio2 mask. A metal electrode is then formed as shown and a CV measurement is made in the region outside the N+ region. The measurement gives C = Cox for all values of applied voltage as shown. Explain what might have gone wrong in this experiment. That is explain why no surface inversion is observed in the CV measurement. Linear Parabolic Model (Deal Grove model) • The basic model for oxidation was developed in 1965 • by Deal and Grove. It has been assumed that an oxide of some thickness xi is already present on the Si surface. It has also been assume that three steps are necessary for oxidation on the silicon surface although only two of them are important. F1 F2 F3 Si+O2→SiO2 Si+2H2O→SiO2+2H2 Deal-Grove relation • Under steady state conditions these three flows must balance, F1 = F2 = F3. In order to find a growth rate we need Henry’s law , which says that concentration of an absorbed species at the surface of a solid is proportional to the partial pressure of the species in the gas just above the solid: CO=HPS = HkTCS (7) • so combining equations (1-7) we can write as • Where h=hG/HkT • The growth rate can be determined by following equation • Where N1 number of molecule of oxygen per unit volume of SiO2 • By using boundary (at time =0, xi=x0)- condition the solution of above differential equation is written as       += hGks DAwhere 112 D xk h K HPC oSS G I ++ = 1 )(0 2 τ+=+ tBAxxo (8) (9)     ++ === D xk h KN PHk dt dx N FR oSS Gso 111 1 2 N DHPB G= B Axx ii += 2 τ The parameters A and B are proportional to diffusitivity and follow an Arrenhious function. τ the shift in time to account for initial oxide thickness. (10) EE 439/539 The Linear and Parabolic rate coefficients (two limiting forms of Deal Grove model) • Case I: For very short oxidation time (thin oxides layer), the rate equation reduced to the linear form • Case II: when t>>τ, the oxide is sufficiently thick, the rate equation reduced to the simple parabolic expression, • B/A and B are often termed the linear and parabolic rate coefficients respectively because of the xo and x2o terms in which they appear. Physically, they represent the contribution of fluxes F3 (interface reaction) and F2 (oxidant diffusion), respectively. SiO2 growth on a bare Si wafer usually starts out with a linear xx versus x, which become parabolic as the oxide thickens. • In fact, B and B/A are normally determine experimentally by extracting them from growth rate. The reason for taking this approach is simply that we usually do not know all the parameters in Grove-Deal model equations. Ks (interface reaction rate constant) is particular contains a lot of “hidden” physics associate with the interface reaction. What we do, however, is compare experimental values of B and B/A with the model equations. To test the reasonableness of the liner parabolic model. )( / )( 0 2 02 τττ +≈⇒+=+⇒+=+ t A Bxt AB x B xtBAxx oo O BttBxt AB x B xo ≈+≈⇒+=+ )()( / 2 0 0 2 ττ Analysis of the rate constants (B and B/A) • Experimentally, it has been found that both B and B/A are well describe by Arrhenious expressions of the form • B=C1exp(-E1/kT) • B/A= C2exp(-E2/kT) • Where E 1 and E2 are the activation energies associated with the physical process that B and B/A represent; C1 and C2 are the preexponential constant. • The physical mechanism responsible for E1 might be the oxidant diffusion through the Sio2. • The physical origin of E2 is likely connected with the interface reaction rate constant Ks. Ks really represent the number of process occurring at the interface. 10 9 B Axx ii += 2 τ )(0 2 τ+=+ tBAxxo EE 439/539 A p-type Si wafer with a resistivity of 10Ωcm is placed in a wet oxygen system to grow a field oxide of 0.45145µm at a 1050C. Determine the time require to Grow the oxide. Problems in Deal Grove model: Initial Oxidation Stage • A major problem with the Deal Grove model was recognized when it was first proposed - it does not correctly model thin O2 growth kinetics (0-30 nm). • Experimentally dry O2 oxides grow much faster for ≅ 200 Å than Deal Grove predicts. • MANY suggestions have been made in the literature about why. None have been widely accepted. • Since modern technologies emphasize this range of oxide thickness for MOSFETs and capacitors, intense work has been done to model the initial rapid stage of oxidation.According to the deal grove model the oxidation rate should apporch at constant value i. e. A B dt dxo t Lim = →0 Instead, the oxidation rate increased by a factor of 4 or more.       +≈ )( τt A Bxo Effect of stress on Oxidation Kinetics • Stress is created by two- dimensional growth of oxide and the resulting volume expansion of the oxidize region. • As the oxide grow the “newly” formed oxide pushes out the “old” oxide which rearranges itself through viscous flow. • Stress occurs typically on curved surfaces, as illustrated for the inside and outside corners of a trench in Si. 2D SiO2 Growth Kinetics Several physical mechanisms are important in explaining these results: • Crystal orientation • 2D oxidant diffusion • Stress due to volume expansion • To model the stress effects, Kao et. al. suggested modifying the Deal Grove parameters. These models have been implemented in modern process simulators and allow them to predict shapes and stress levels for VLSI structures. EE 439/539 Fick’s first law diffusion equation (cont.) • Fick’s first law is mathematically described by the equation, • Proportionality constant is the diffusivity D in cm 2 sec -1 . D is related to atomic hops over an energy barrier (formation and migration of mobile species) and is exponentially activated. D is isotropic in the silicon lattice. • Negative sign indicates that the flow is down the concentration gradient. x txCDF ∂ ∂ −= ),( x txCDJ ∂ ∂ −= ),( Analytic Solutions of Fick’s Laws: Limited Source: • Consider a fixed dose Q, introduced as a delta function at the origin. • The solution that satisfies Fick’s second law is • Important consequences: 1. Dose Q remains constant 2. Peak concentration decreases as 1/ √t 3. Diffusion distance from origin increases as 2 √Dt Introduced a spike of dopant in the middle of Lightly doped region. The factor 2√Dt is often termed as the Diffusion length (how far the dopant has diffused?). Analytic Solutions of Fick’s Laws: Limitted Source Near A Surface • This solution is also called drive in diffusion. In this case initial amount of impurity QT is introduced into the wafer subject the boundary condition that QT is fixed. Analytic Solutions of Fick’s Laws: constant Source Near A Surface • This condition is correspond to putting a heavily doped epitaxial layer on a lightly doped wafer. • The solution which satisfies Fick’s law is given by , • Important consequences of Error function solution: • Symmetry about mid-point allows solution for constant surface concentration to be derived. • Dose beyond x=0 continues to increase with annealing time. EE 439/539 Intrinsic diffusion coefficients Intrinsic dopant diffusion coefficients are found to be of the form, Where is the activation energy of the neutral vacancy and Do is the measure of the frequency with which an atom “attempts” to make a jump over the barrier (1013-1014Hz). The exponential term which represent the probability that an atom will have an energy equal to or in access of the activation energy. EA Note the "slow" and "fast" diffusers. Solubility is also an issue in choosing a dopant for a particular application. 3.2 Atomic Scale Diffusion: Fair’s vacancy model • Many effects that are very important experimentally, cannot be explained by the macroscopic models discussed so far. Thus we need to look deeper at atomic scale effects. • In the vacancy model, vacancy can be neutral (Vo), positively charged by donating an electron (V+), double positively charged by donating two electrons (V++), negatively charged by accepting an electron (V-), double negatively charged by accepting two electrons (V=). However, the probability for high level charged is very low. Due to these probabilities, the most general expression for the diffusion coefficient in the vacancy model is given by, ........... 2 2 3 3 2 2 D n pD n pD n nD n nD n nDD iiiii o       +++      +      ++= +−−− For substrate with excess free Electron (n-type), positive charge term can be neglected and for substrate with excess free holes(p-type) the negati charge terms can be neglected. Concentration Dependent Diffusivity ........... 2 2 3 3 2 2 D n pD n pD n nD n nD n nDD iiiii o       +++      +      ++= +−−− The dash line show the erfc profiles. The solid lines are numerical simulation which agree with experimental results At high doping concentrations, the diffusivity appears to increase. Fick's equation must then be solved numerically since D ≠ constant. EE 439/539 Example ........... 2 2 3 3 2 2 D n pD n pD n nD n nD n nDD iiiii o       +++      +      ++= +−−− kTEo o o oaeDD /−−= The surface of a silicon wafer has a region that is uniformly doped with boron at the concentration of 1018 cm-3. This layer is 20 angstroms thick (1 angstrom = 10-4 micrometer = 10-8 cm). The entire wafer, including this region, is uniformly doped with arsenic at a concentration of 1015cm-3. The surface of the wafer is sealed and it is heated at 1000 degrees Celsius for 30 minutes. Assume intrinsic diffusion. a) Find the concentration of boron at the surface after the anneal. b) Find the junction depth (boron concentration equal to arsenic concentration) after the anneal. Solution: 3.6a) This is a drive-in diffusion sec 10*0.9* sec 41.0* sec 037.0 ,*),( 2 2 151273/46.3 2 1273/46.3 2 4/ cmecmecmD wheree Dt QtxC KeVKeV DtxT −−− − =+= = π At the surface of the wafer, x=0 31610*8.2),0( −== cm Dt QtC T π 3.6b) m DtC QDtx sub T J µπ 15.0ln*4 =         = EE 439/539 Example : Mass Resolution       +−= φφδ sincos1 2 1 R L M M R D 5 Implant Profiles • Ion implantation is a random process. • High energy ions (1- 1000keV) bombard the substrate and lose energy through nuclear collisions and electronic drag forces. 6 Range distribution • The average depth below the surface an ion penetrate is called the mean projected range RP. This depth is typically shorter than the actual distance the ion travels. • Some ion stop at a depth smaller than RP, and other at a depth larger than RP. The distribution about RP can be approximated by a Gaussian with a standard deviation, or straggle, ∆RP can be estimated by, • Where Mi and Mt are the masses for incident and target ion • The implanted ion also scatter laterally around the impact point, which can also approximated by Gaussian distribution with transverse straggle, ∆RT.         + ≅∆ ti ti pp MM MM RR 3 2 EE 439/539 Mathematical model for ion implantation • Profiles can often be described by a Gaussian • distribution, with a projected range and standard deviation. (200KeV implants shown in the Fig.)         ∆ − − ∆ = p p p R Rx R xN 2 2 2 )( exp 2 )( π φ Where RP is the project range and ∆RP is the standard deviation of the projected range and φ is dose. The total number of ion implanted (dose) can be also written as This provide a useful relationship between The dose and the peak concentration of the Implant. ppCR∆= πφ 2 CP is the peak concentration. 7 Fig. 6.20el Range and implanted struggle (∆RP) EE 439/539 A 30-KeV implant of B11 is done into a bare silicon The dose is 1012cm-2 (a) What is the depth of peak of implanted profile? (b) What is the concentration At this depth? © what is the concentration at depth of 3000Ao? (d) The measured concentration is found to be an order of magnitude larger than the value predicted in part © although the profile agrees with answers (a) and (b). Give a possible explanation, assuming that the measured value is correct. Example Lateral Spread of Implanted Ions • When a mask is used to implant selective regions of the wafer, there is also lateral scattering perpendicular to the path of the incident beam that causes a transverse spread, ∆RT, of implanted ion from the mask edge. • As the dimension of the modern MOS devices shrink, ∆RT. becomes very important. Deviation from the Gaussian Theory (Skewness) • When light ions such as boron, impact atoms of the silicon target, they experience a relatively large amount of backward scattering and fill in the distribution on the front side of the peak. • Heavy atoms such as antimony, experience a large amount of forward scattering and tend to fill in the profile on the substrate side of the peak. • The different skewnress can be visualized by thinking of forward momentum. • A number of model has been proposed to explain this behavior. The most common one is known as Pearson Type –IV. Implants in Real Silicon - Channeling • At least until it is damaged by the implant, Si is a crystalline material. • Channeling can produce unexpectedly deep • profiles. EE 439/539 Transient Enhanced Diffusion (TED) • TED occurs when an attempt is made to anneal implant damage and restore the lattice to its crystalline perfection. It consist of a burst of diffusion many thousand of time faster than what is normally absorb for similar anneal when no implant damage is present The basic model for TED assumes that all the implant damage recombines rapidly, leaving only 1 interstitial generated per dopant atom when the dopant atom occupies substitutional site (the +1 model) [Giles]. THIN FILM DEPOSITION - Introduction Many films, made of many different materials are deposited during a standard CMOS process. These layers include silicon dioxide, silicon nitride, poly silicon and metal. • In this set of notes we describe the requirements, methods and equipment used to deposit these thin films. • Requirements or desirable traits for deposition: • 1. Desired composition, low contaminates, good electrical and mechanical properties. • 2. Uniform thickness across wafer, and wafer-to wafer. • 3. Good step coverage (“conformal coverage”). • 4. Good filling of spaces. • 5. Planarized films . Issue related to thin film and their deposition Quality of the deposited film Uniform thickness across a wafer Chance of high resistivity Mechanical cracking Filling contact hole with a metal Filling between metal lines with an oxide Incomplete filling leading to a void In dielectric between the lines. A void in a metal layer can lead to High sheet resistance and in a dielectric can result in creaking problem. EE 439/539 Aspect ratio • An important parameter that can effect filling and bottom coverage is the aspect ratio of a feature, defined as, • w hAR = A deep narrow contact hole Would have a large aspect ratio And would be harder to fill. Historical Development and Basic Concepts • Two main types of deposition methods have been developed and are used in CMOS technology: • Chemical Vapor Deposition (CVD) - APCVD, LPCVD, PECVD, HDPCVD • Physical Vapor Deposition (PVD) - evaporation, sputter deposition Atmospheric Pressure Chemical Vapor Deposition ( APCVD) • Steps involved in a CVD process: • 1. Transport of reactants to the deposition region. • 2. Transport of reactants from the main gas stream through the boundary layer to the wafer surface. • 3. Adsorption of reactants on the wafer surface. • 4. Surface reactions, including: chemical decomposition or reaction, surface migration to • attachment sites (kinks and ledges); site incorporation; and other surface reactions (emission • and redeposition for example). • 5. Desorption or reemission of by-products. • 6. Transport of by-products through the boundary layer. • 7. Transport of by-products away from the deposition • region. Kinetics of CVD thin film deposition (cont.) • In steady state • F=F1=F2 The growth rate (growth velocity) is now given by, where N is the number of atoms incorporated per unit volume in the film (5 x 1022 cm-3 for the case of epitaxial Si deposition) and Y is the mole fraction (partial pressure/total pressure) of the incorporating species , can be written as Y=CG/CT=PG/Ptotal Where CT is the concentration of all the gas molecules in the gas phase (i.e. SiCl4, H2) Note the similarity of this analysis to the Deal Grove oxidation model (Chapter 6). EE 439/539 Limiting cases of growth velocity 1. If kS << hG , then we have the surface reaction controlled case: 2. If hG << kS, then we have the mass transfer, or gas phase diffusion controlled case: Arrhenius plot of the growth velocity vs 1/T for CVD process • The surface term is Arrhenius with Ea depending on the particular reaction (1.6 eV for single crystal silicon deposition). • hG is ~ constant (diffusion through boundary layer). • Key points: • kS limited deposition is VERY temp sensitive. • hG limited deposition is VERY geometry (boundary layer) sensitive. Si epi deposition often done at high T to get high quality single crystal growth. ∴hG controlled. ∴horizontal reactor configuration. Polysilicon is usually deposited at lower temperature and in the surface reaction regime. Experimental data Doping and Autodoping • Thin film deposited by CVD can be doped while grown by adding controlled amounts of the dopant compounds to the gas stream. • Typical dopant sources are phosphine (PH3), arsine (AsH3), and diborane (B2H6). • In addition, unintentional dopants are introduced from the substrate either by solid state diffusion or by evaporation. EE 439/539 Sputter Deposition • Uses plasma to sputter target, dislodging atoms which then deposit on wafers to form film. • Higher pressures than evaporation - 1-100 mtorr. • Better at depositing alloys and compounds than evaporation. Typical sputtering energy range from 0.5KeV- 5 KeV. Plasma structure and voltage distribution in DC sputter system • The plasma contains ~ equal numbers of positive argon ions and electrons as well as neutral argon atoms. • Most of voltage drop of the system (due to applied DC • voltage, Vc) occurs over cathode sheath. • Ar+ ions are accelerated across cathode sheath to the • negatively charged cathode, striking that electrode • (the “target”) and sputtering off atoms (e.g. Al). • These travel through plasma and deposit on wafers • sitting on anode. Important process in Sputter deposition A minimum energy on the order of 10- 20eV, is needed to sputter an atom. Sputtering targets are generally large and provide a wide range of arrival angles in contrast to a point source. EE 439/539 asymmetric depositions • Asymmetric deposition means that thicker deposition occurs on one side of a feature (a step, for example) than the other Target Wafer Wafer Target How can we avoid asymmetric deposition? Is there another way to reduce any asymmetry ? 9.13. How does the ability to fill the bottom of a narrow trench using sputter deposition change as the target is moved further away from the wafer? Neglect any gas phase collision effects. Answer: The further away the target, the narrower the arrival angle distribution, similar to making the target smaller. So n is greater and better filling of the bottom of a narrow trench is achieved. RF Sputter Deposition • For DC sputtering, target electrode is conducting. • To sputter dielectric materials use RF power source. • Due to slower mobility of ions vs. electrons, the plasma biases positively with respect to both electrodes. (DC current must be zero.)∴ continuous sputtering. • •When the electrode areas are not equal, the field must be higher at the smaller electrode (higher current • density), to maintain overall current continuity. • Thus by making the target electrode smaller, sputtering occurs "only" on the target. • Wafer electrode can also be connected to chamber walls, further increasing V1/V2. Ionized Sputter Deposition or HDP Sputtering • In some systems the depositing atoms themselves are ionized. An RF coil around the plasma induces collisions in the plasma creating the ions. • This provides a narrow distribution of arrival angles which may be useful when filling or coating the bottom of deep contact hole. Little deposition at the bottom of the hole due to shadowing effect. EE 439/539 . Calculate the mean free path of a particle in the gas phase of a deposition system and estimate the number of collisions it experiences in traveling from the source to the substrate in each of the cases below. Assume that in each case the molecular collisional diameter is 0.4 nm, the source-to-substrate distance is 5 cm, and that the number of collisions is approximately equal to the source-to-substrate distance divided by the mean free path. a. An evaporation system in which the pressure is 10-5 torr and the temperature is 25˚C. b. A sputter deposition system in which the pressure is 3 mtorr and the temperature is 25˚C. c. An LPCVD system in which the pressure is 1 torr and the temperature is 600˚C. d. An APCVD system in which the pressure is 1 atm and the temperature is 600˚C. 9.11 The mean free path of a gas particle is (Eqn. 9.26) λ = kT 2πd2P where k = 1.36x10-22 cm3 atm K-1, T is the temperature in K, d is the collision diameter of the molecule in cm (approximately 4x10-8 cm for most molecules of interest), and P is the pressure in atm. The # collisions is approximately equal to the source-to- substrate distance divided by the mean free path in each case. Plugging in the numbers gives: λ(in cm) = kT 2d2 P = 1.36x10−22 cm3 ⋅ atm ⋅K−1 ∗T(K) 2π 4x10−8 cm( )2 P(torr)760torr / atm = 1.45x10−5 T(K) P(torr) a. 433 cm, 1.2x10-2 collisions; b. 1.44 cm, 3.5 collisions; c. 0.013 cm, 392 collisions; d. 1.7x10-5 cm, 3.0x105 collisions Summary of the key ideas • In this chapter we have examined how thin films are deposited as part of the fabrication of IC. • Important issues in thin film deposition include physical and chemical properties of the films, step converge and filling of the holes or trenches. • In the simple model for CVD presented, the deposition process is seen to be limited by surface reaction or by mass transfer. • At low pressure the mass transfer is not a limiting step, and the surface reaction become rate limiting. • In PVD arrival angle distribution of the source material at the wafer surface is important. • Shadowing by topographical features can be very important in PVD method. • Concurrent sputtering and redeposition of the material along with the direct deposition of ionized species can lead to good gap or hole filling of relatively high aspect ration features. EE 439/539 Ion Enhanced Etching • Figure shows etch rate of silicon as XeF2 gas (not plasma) and Ar+ ions are introduced to the silicon surface. • Only when both are present • does appreciable etching occur. • Etch profiles can be very anisotopic, and selectivity can be good. • Many different mechanisms proposed for this synergistic etching between physical and chemical mechanisms proposed for synergistic etching • Inhibitor could be either direct byproduct of etch process, or indirect byproduct (such as polymer formation from C in gas or from photoresist). • Whatever the exact mechanism (multiple mechanisms may occur at same time): • the two components act in series. • get anisotropic etching and little undercutting because of directed ion flux. • get selectivity due to chemical component. • ∴many applications in etching today. Etching by radical is negligible Summary of plasma system and mechanism Summery of trends of different etch system EE 439/539 BACKEND TECHNOLOGY-11 • Backend technology: fabrication of interconnects and the dielectrics that electrically and physically separate them. • More metal interconnect levels increases circuit • functionality and speed. • Local interconnects (polysilicon, silicides, TiN) versus global interconnects (usually Al). Early structures were very simple by today's standards. Issues in VLSI Metallization Speed: switching speed, RC delay Intensity: electromigration (I), electric breakdown (V) Stability: contact interface, stable I-V characteristics Voltage drop: IR drop reduces voltage on transistor Area: connection wires have to be narrow as device density increases Speed limitations: next generation technology trends • The speed limitations of interconnects can be estimated fairly simply. • R=ρLW/H • C = Kox εo WL / xox+ Ko xεo H L/ Ls • Where Kox is the dielectric constsant. • The tolat RC delay associated with global interconnects • is: • To keep the analysis simple we assume that xox, H, as well as Ls and W, are equal to minimum feature size thus the above equation can be written in terms of the area A of the chip 2 min )( 89.0 F AK ooxL ρετ = The goal is to decrease τL, or at least to keep it from increasing too much as some of the dimension change. EE 439/539 2 min )( 89.0 F AK ooxL ρετ = Recent analysis by Bohr based on Intel's technology agree with the qualitative predictions of this simple analysis Why Aluminum? • Low resistivity Al at room temperature (2-3µΩcm). • It adheres (hold fast or stick by) well to Si and SiO2. • It makes good electric Ohmic contact to heavily doped Si • It react with SiO2 even at low T, forming a thin layer of Al2O3 at the interface, which act as a glue layer to bind the Al to the SiO2. • In case of Al-to-Si contact, the Al reduce any native oxide on top of Si, which could prevent ohmic contact. • Its presence assist the annealing out of interface traps at the Si-SiO2 interface., presumably by converting H2O to free H, which passivate the traps. Spiking problem • Because Si has a significant solubility in Al, e.g. ~1% at 450oC, heat treatment result in dissolution of Si, which tends to proceed more slowly along (111) than (110) or (100) planes. • This creates voids in the crystal into which Al precipitates and form conductive spikes (0.2-1µm) that can cause high leakage or shorts in shallow junctions. Methods used to reduce spiking One solution to the Al spiking problem is to use Al films that already have Si in them (Al-Si alloy). Therefore, the solubility requirement is already fulfilled. In this way spiking problem, reduced but another arises. • Widely used, but Si can precipitate when cooling down, leaving Si nodules. Better solution: use barrier layer(s). Ti or TiSi2 for good contact and adhesion, TiN for barrier TiSi2/TiN is not the only choice, various barrier option are available. , .