Computer Architecture and Organization: An Introduction to CA and CO, Slides of Software Engineering

Download Computer Architecture and Organization: An Introduction to CA and CO and more Slides Software Engineering in PDF only on Docsity! Computer Architecture and Organization 1 CHAPTER 1: INTRODUCTION Computer Architecture and Organization Computer Architecture and Organization 2 LEARNING OBJECTIVES  Know the difference bin CA & CO  Explain the general functions and structure of a digital computer.  Present an overview of the evolution of computer technology  Understand the key performance issues that relate to computer design. Computer Architecture and Organization 5 DIFFERENCE BETWEEN CA & CO Computer Architecture Computer Organization Higher level Lower level (microarchitecture) Visible and very important for programmer Not so important for programmers Logical components (Instruction set, Addressing modes, Data types) Physical components (circuit design, signals, peripherals, adders) What to do? (instruction set) How to do? (implementation of the architecture) 6 ARCHITECTURE & ORGANIZATION …  All Intel x86 family share the same basic architecture  The IBM System/370 family share the same basic architecture  This means the same software can be used on different models, only the hardware changes for performance improvement.  This gives code compatibility  At least backwardsComputer Architec ure nd Organization 7 STRUCTURE & FUNCTION  Structure is the way in which components relate to each other  Function is the operation of individual components as part of the structure  All computer functions are:  Data processing  Data storage  Data movement  Control Computer Architecture and Organization 10 STRUCTURE - TOP LEVEL Computer Architecture and Organization Computer Main Memory Input Output Systems Interconnection Peripherals Communication lines Central Processing Unit Computer 11 STRUCTURE - THE CPU Computer Architecture and Organization Computer Arithmetic and Login Unit Control Unit Internal CPU Interconnection Registers CPU I/O Memory System Bus CPU 12 STRUCTURE - THE CONTROL UNIT Computer Architecture and Organization CPU Control Memory Control Unit Registers and Decoders Sequencing Logic Control Unit ALU Registers Internal Bus Control Unit 15 BRIEF DESCRIPTION OF THE IAS COMPUTER  The memory of the IAS consists of storage locations, called words, of 40 binary digits (bits) each.  Both data and instructions are stored there.  Numbers are represented in binary form, and each instruction is a binary code. Computer Architecture and Organization 16 IAS MEMORY FORMAT  Each number is represented by a sign bit and a 39-bit value.  A word may also contain two 20-bit instructions, with each instruction consisting of 8-bit operation code (opcode) and 12-bit address Computer Architecture and Organization 17 IAS MAIN REGISTERS  Memory buffer register (MBR):Contains a word to be stored in memory or sent to the I/O unit, or is used to receive a word from memory or from the I/O unit.  Memory address register (MAR):Specifies the address in memory of the word to be written from or read into the MBR.  Instruction register (IR):Contains the 8-bit opcode instruction being executed.  Instruction buffer register (IBR):Employed to hold temporarily the right hand instruction from a word in memory.  Program counter (PC):Contains the address of the next instruction pair to be fetched from memory.  Accumulator (AC) and multiplier quotient (MQ): Employed to hold temporarily operands and results of ALU operations. For example, the result of multiplying two 40-bit numbers is an 80-bit number; the most significant 40 bits are stored in the AC and the least significant in the MQ. Computer Architecture and Organization 20 IAS INSTRUCTION SET The IAS computer had a total of 21 instructions, which can be grouped as follows:  Data transfer: Move data between memory and ALU registers or between two ALU registers.  Unconditional branch: Normally, the control unit executes instructions in sequence from memory. This sequence can be changed by a branch instruction, which facilitates repetitive operations.  Conditional branch: The branch can be made dependent on a condition, thus allowing decision points.  Arithmetic: Operations performed by the ALU.  Address modify: Permits addresses to be computed in the ALU and then inserted into instructions stored in memory. This allows a program considerable addressing flexibility. Computer Architecture and Organization 21 THE SECOND GENERATION : TRANSISTORS  Transistor Based Computers  More complex arithmetic and logic units and control units,  The use high-level programming languages and software provided the ability to load programs,(beginning of OSes)  Data channels:-independent I/O module with its own processor & Instruction set. -relieves the CPU of a considerable processing burden.  Multiplexor :- termination point for data channels, the CPU, and memory. - schedules access to the memory from the CPU and data channels Computer Architecture and Organization 22 TRANSISTORS  Replaced vacuum tubes  Smaller  Cheaper  Less heat dissipation  Solid State device  Made from Silicon  Invented 1947 at Bell Labs  William Shockley et al. Computer Architecture and Organization 25 MOORE’S LAW  Gordon Moore – co-founder of Intel  Number of transistors on a chip will double every year  Since 1970’s development has slowed a little  Number of transistors doubles every 18 months  Cost of a chip has remained almost unchanged  Consequence of Moore’s Law  Higher packing density means shorter electrical paths, giving higher performance  Smaller size gives increased flexibility  Reduced power and cooling requirements  Fewer interconnections increases reliability Computer Architecture and Organization 26 IBM 360 SERIES  1964  Replaced (& not compatible with) 7000 series  First planned “family” of computers  Similar or identical instruction sets  Similar or identical O/S  Increasing speed  Increasing number of I/O ports (i.e. more terminals)  Increased memory size  Increased cost Computer Architecture and Organization 27 DEC PDP-8  1964  First minicomputer (after miniskirt!)  Small enough to sit on a lab bench  $16,000  $100k+ for IBM 360 Computer Architecture and Organization CONT… MICROCOMPUTER AND INTERFACING CSE3314 30  Gordon Moore, cofounder of Intel  “The number of transistors on a microchip doubles every two years, though the cost of computers is halved.” 1965: Moore’s Law CONT… MICROCOMPUTER AND INTERFACING CSE3314 31  The World's First Microprocessor  Was designed for the US Navy F14A “TomCat” fighter jet 1968-1970: “Tomcat” CONT… MICROCOMPUTER AND INTERFACING CSE3314 32  The first commercially available µP  4 bit processor, made by Intel,  had 2300 transistors,  speed up to 740 KHz 1971: Intel 4004 CONT… MICROCOMPUTER AND INTERFACING CSE3314 35  16 bit processor with 20 bit address bus  Speed: 5 MHz to 10 MHz  29,000 Transistors  1979: 8088 a slightly modified chip with an external 8-bit data bus  8088 (used in the IBM PC)  8086 gave rise to the x86 architecture, which eventually became Intel's most successful line of processors 1978: Intel 8086/8088 CONT… MICROCOMPUTER AND INTERFACING CSE3314 36  16 bit processor with 24 bit address bus  Speed: 4 MHz to 25 MHz  134,000 Transistors  16 MB of physical MEM and 1 GB of virtual mem  IBM PC/AT in 1984, IBM PS/2 Model 50 and 60 1982: Intel 80286 CONT… MICROCOMPUTER AND INTERFACING CSE3314 37  32 bit processor with 32 bit address bus  Speed: 12 MHz to 40 MHz  275,000 Transistors  up to 4 GB of memory.  Memory paging and enhanced I/O permission features 1985: Intel 80386 40 LOGIC AND MEMORY PERFORMANCE GAP Computer Architecture and Organization 41 SOLUTIONS  Increase number of bits retrieved at one time  Make DRAM “wider” rather than “deeper” by using wide bus data paths  Change DRAM interface  including a cache or other buffering scheme on the DRAM chip  Reduce frequency of memory access  This includes the incorporation of one or more caches on the processor chip as well as on an off-chip cache close to the processor chip.  Increase interconnection bandwidth  High speed buses and Hierarchy of buses Computer Architecture and Organization Computer Architecture and Organization 42 HOW TO INCREASE PROCESSOR SPEED  Increase the hardware speed of the processor.  Shrinking the size of the logic gates and packed together more tightly and increase clock rate  An increase in clock rate means that individual operations are executed more rapidly.  Increase the size and speed of caches  Dedicating a portion of the processor chip itself to the cache, cache access times drop significantly.  Make changes to the processor organization and architecture  Using parallelism (instruction pipelining and superscalar ) 45 NEW APPROACH – MULTIPLE CORES  A multi-core processor is a computer processor on a single IC with two or more separate processing units, called cores, each of which reads and executes program instructions.  Single processor can run instructions on separate cores at the same time, increasing overall speed for programs.  In particular, possible gains are limited by the fraction of the software that can run in parallel simultaneously on multiple cores Computer Architecture and Organization 46 PART 2 Chapter 1 Computer Architecture and Organization LEARNING OBJECTIVES  Understand the basic elements of an instruction cycle and the role of interrupts.  Describe the concept of interconnection within a computer system. Computer Architecture and Organization 47 Computer Architecture and Organization 50 HOW COMPUTER EXECUTE INSTRUCTIONS?  Two steps:  Fetch  Execute  The instruction execution may involve several operations and depends on the nature of the instruction Instruction Cycle 51 INSTRUCTION CYCLE Computer Architecture and Organization  The processing required for a single instruction is called an instruction cycle  Fetch cycle  Program Counter (PC) holds address of next instruction to fetch  Processor fetches instruction from memory location pointed to by PC  Increment PC  Unless told otherwise  The Opcode of the Instruction loaded into Instruction Register (IR)  Execute cycle  Processor interprets instruction and performs required actions 52 CONT… Computer Architecture and Organization In general, these actions fall into four categories  Processor-memory  data transfer between CPU and main memory  Processor I/O  Data transfer between CPU and I/O module  Data processing  Some arithmetic or logical operation on data  Control  Alteration of sequence of operations  e.g. jump Combination of above Computer Architecture and Organization 55 CONT…  Some older processors, included instructions that contain more than one memory address in a single instructions  Thus, the execution cycle for a particular instruction on such processors could involve more than one reference to memory.  For example, the PDP-11 processor ADD B,A instruction  Also, instead of memory references, an instruction may specify an I/O operation.  With these additional considerations in mind, Instruction cycle state diagram provides a more detailed look at the basic instruction cycle  For any given instruction cycle, some states may be null and others may be visited more than once. Computer Architecture and Organization 56 PDP-11 instruction ADD A,B results in the following sequence of states: iac, if, iod, oac, of, oac, of, do, oac, os. 57 INTERRUPTS  Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing  Program  e.g. overflow, division by zero  Timer  Generated by internal processor timer  Used in pre-emptive multi-tasking  I/O  from I/O controller  Hardware failure  e.g. memory parity error Computer Architecture and Organization Computer Architecture and Organization 60 TRANSFER OF CONTROL VIA INTERRUPTS Fetch cycle Execute cycle Interrupt cycle Interrupts disabled Execute e et instruction Interrupts s process interrupt enabled P Figure 3.9 Instruction Cycle with Interrupts Computer Architecture and Organization Computer Architecture and Organization 62 MULTIPLE INTERRUPTS  Two approaches  A disabled interrupt  Simply means that the processor can and will ignore that interrupt request signal. If an interrupt occurs during this time, it generally remains pending and will be checked by the processor after the processor has enabled interrupts.  The drawback to the preceding approach is that it does not take into account relative priority or time-critical needs.  A second approach is to define priorities for interrupts and to allow an interrupt of higher priority to cause a lower-priority interrupt handler to be itself interrupted Computer Architecture and Organization 65 INSTRUCTION CYCLE STATE DIAGRAM, WITH INTERRUPTS Computer Architecture and Organization 66 INTERCONNECTION STRUCTURES  A computer consists of a set of components or modules of three basic types (processor, memory, I/O) that communicate with each other.  The collection of paths connecting the various modules is called the interconnection structure.  The design of this structure will depend on the exchanges that must be made among modules. Computer Architecture and Organization 67 MEMORY  Typically, a memory module will consist of N words of equal length.  Each word is assigned a unique numerical address (0, 1, .., N-1).  A word of data can be read from or written into the memory.  The nature of the operation is indicated by read and write control signals.  Th locatio for the operation is specified by an address. Computer Architecture and Organization 70 BUS INTERCONNECTION  Bus is a shared communication pathway connecting two or more devices  Usually broadcast  Often grouped  A number of channels in one bus  e.g. 32 bit data bus is 32 separate single bit channels  Only one device at a time can successfully transmit  Power lines may not be shown  Computer systems contain a number of different buses  A bus that connects major computer components (processor, memory, I/O) is called a system bus.  Bus lines can be classified into three functional groups: data, address, and control lines. Computer Architecture and Organization 71 DATA BUS  The data lines (Data Bus) provide a path for moving data among system modules.  The width of the data bus may consist of 32, 64, 128, or even more separate lines.  The number of lines determines how many bits can be transferred at a time.  The width of the data bus is a key factor in determining overall system performance.  For example, if the data bus is 32 bits wide and each instruction is 64 bits long, then the processor must access the memory module twice during each instruction cycle. Computer Architecture and Organization 72 ADDRESS BUS  The address lines are used to designate the source or destination of the data on the data bus.  For example, if the processor wishes to read a word (8, 16, or 32 bits) of data from memory, it puts the address of the desired word on the address lines.  The width of the address bus determines the maximum possible memory capacity of the system  Furthermore, the address lines are generally also used to address I/O ports.  Typically, the higher-order bits are used to select a particular module on the bus, and the lower-order bits select a memory location or I/O port within the module.  For example, on an 8-bit address bus, address 01111111 and below might reference locations in a memory module (module 0) with 128 words of memory, and address 10000000 and above refer to devices attached to an I/O module (module 1). BUS INTERCONNECTION SCHEME CPU Memory eee Memory VO Vo Co ntrol Lines Address Lines Data Lines Computer Architecture and Organization Bus Computer Architecture and Organization 76 SINGLE BUS PROBLEMS  Lots of devices on one bus leads to:  Propagation delays  Long data paths mean that co-ordination of bus use can adversely affect performance  Most systems use multiple buses to overcome these problems TRADITIONAL (ISA) (WITH CACHE) Processor Local Bus Cache Local WO Main controller Memory System Bus Network Expansion SCSI bus interface Modem Serial Expansion Bus Computer Architecture and Organization