Download Computer Architecture and Design: Homework 7 Solutions for ELEC 5200-001/6200-001 - Prof. and more Assignments Computer Architecture and Organization in PDF only on Docsity! ELEC 5200-001/6200-001 Computer Architecture and Design Spring 2007 Homework 7 Solutions Assigned 4/2/07, due 4/11/07 Problem 1: Single-cycle datapath Modern CMOS technologies allow dual supply voltage operation. This means cores operating at different supply voltages can be integrated on the same chip. Following cores are available for implementing a datapath chip: Core function VDD = 2V VDD = 1V Delay Energy per input Delay Energy per input Memory 100ps 9μJJ 200ps 3μJJ Register file 50ps 9μJJ 100ps 3μJJ ALU 50ps 9μJJ 100ps 3μJJ a. What is the minimum clock cycle time for a single-cycle MIPS datapath when all units operate with 2V supply? b. What is the CPI (cycles per instruction) rating for this single-cycle datapath? c. Can you use dual-voltage operation to reduce the power consumption of the single-cycle datapath without reducing its performance? Solution: a. Clock cycle time is determined by the lw instruction that takes the longest to execute: Time(lw) = Time(IF) + Time(ID+Reg.File) + Time(ALU) + Time(MemRead) + Time(Reg.FileWrite) = 100+50+50+100+50 = 350ps The clock cycle time should not be less than 350ps. b. Single-cycle data-path completes one instruction per cycle: CPI = 1. c. All reduced voltage cores have longer delays. Hence, the power consumption cannot be reduced without lowering the performance. Problem 2: Multi-cycle data-path a. What is the minimum clock cycle time for a multi-cycle MIPS datapath implemented with cores given in Problem 1 when a single supply voltage of 2V is used? b. Assuming that all five types of instructions (lw, sw, R-type, branch, and jump) occur with equal frequency what will be the CPI for this multi-cycle datapath? c. Explain whether you can use the low-voltage cores of Problem 1 in a dual-voltage operation to save power without affecting the performance of the multi-cycle data-path? How much energy will each type of instruction save by such a design? Solution: a. For a multi-cycle data-path, the clock cycle time should not be less than the time taken by the slowest hardware unit. Since memory operations take 100ps, which is the most, the clock-cycle time should be at least 100ps. b. Numbers of cycles used by various instructions are 5 for lw, 4 for sw and R-type, and 3 for branch and jump. Since all instructions occur with equal frequency, the average number of cycles taken by an instruction is, CPI = (5+4+4+3+3)/5 = 3.8 c. For low-voltage operation, memory takes more time than the clock cycle time. Hence we must use the higher voltage memory core. Low-voltage cores for register file and ALU can be used without affecting the performance. Energy savings are shown in the following table, which gives the energy consumption for memory, register file and ALU operations of various instructions on the single- supply and dual-supply datapaths. Note that cycles 1 (fetch) and 2 (decode) are independent of the instruction. Instruction Hardware usage Single supply, VDD = 2.0V Dual supply, VDD = 2.0V and 1.0V Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle5 lw Mem. ALU Reg. ALU ALU Mem. Reg. 63μJJ 33μJJ sw Mem. ALU Reg. ALU ALU Mem. 54μJJ 30μJJ R-type Mem. ALU Reg. ALU ALU Reg. 54μJJ 24μJJ B-type Mem. ALU Reg. ALU ALU 45μJJ 21μJJ J-type Mem. ALU Reg. ALU 36μJJ 18μJJ
