Download Solutions on Computer Architecture and Design - Homework 9 | ELEC 5200 and more Assignments Computer Architecture and Organization in PDF only on Docsity! ELEC 5200-002/6200-002 Computer Architecture and Design Fall 2006 Homework 9 Solutions Assigned 12/1/06, due 12/6/06 Problem 1: Consider a five-stage pipelined MIPS processor that contains no hardware to handle hazards. Give an example of each type of hazard and explain how the software will handle it. Answer: Three types of hazards are possible in a pipeline processor: 1. Structural hazard – This occurs due to a resource conflict. In the pipeline, the memory is accessed every cycle for fetching instructions. However, in the fourth cycle after their execution begins, lw and sw perform memory operations. If a single memory is used and allows only one operation (either read for instruction fetch, or read for lw, or write for sw) at a time, then the resource conflict will require a one cycle delay in instruction fetch. To handle this hazard, the compiler must insert a no-op instruction as a fourth instruction after each lw and sw. In general, separate instruction and data caches, and dual-port memories are typical hardware solutions for the structural hazard problem. 2. Data hazard – Contents of a register have not been updated before the clock cycle in which they are needed. Consider the pair of MIPS instructions: add $s1, $s2, $s3 % add s2 and s3, write sum to s1 add $t1, $s1, $s2 % add s1 and s2, write sum to t1 Suppose the first instruction is fetched in cycle 1. Then it will write the sum to s1 in cycle 5. However, the second instruction, fetched in cycle 2, will add s1 in cycle 4. To resolve this hazard, the compiler must delay the second instruction by two cycles, i.e., insert two no-ops. This action is taken whenever an R-type or a lw instruction is followed by another instruction such that the destination register of the first instruction is a source register for the second instruction. Compiler can sometimes resolve this hazard by reordering the code such that no-ops are avoided or reduced. 3. Control hazard – When the sequence of instruction execution is altered by an instruction, other instructions in the pipeline become invalid. A conditional branch instruction is an example. Normally, a branch instruction will decide in the third cycle whether or not the content of PC should be changed. Thus, the compiler must insert adequate number of no-ops after each branch instruction to ensure that either the correct instruction, or no instruction, is fetched.
