Computer Architecture and Design Homework 8 Solutions: Datapath Latency and Throughput - P, Assignments of Computer Architecture and Organization

Download Computer Architecture and Design Homework 8 Solutions: Datapath Latency and Throughput - P and more Assignments Computer Architecture and Organization in PDF only on Docsity! ELEC 5200-002/6200-002 Computer Architecture and Design Fall 2006 Homework 8 Solutions Assigned 11/6/06, due 11/13/06 Problem 1: Define datapath latency. What is the pipeline latency for: (a) Single-cycle datapath with cycle time of T1 (b) Pipelined datapath with n stages and a cycle time Tn (c) Which of these two datapaths has lower latency? Why? Solution: Datapath latency is the time to execute an (isolated) instruction. (a) Single-cycle datapath latency = T1 (b) Latency of n-stage pipeline = n ×Tn (c) Single-cycle datapath has a lower latency, because its cycle time (T1) can be made less than n times the cycle time of the pipilined datapath (Tn). Problem 2: Define the throughput of a datapath. Derive the throughputs of the following datapaths in MIPS (million instructions per second) for long streams of instructions: (a) Single-cycle datapath with cycle time of T1 (b) Pipelined datapath with n stages and a cycle time Tn (c) Which of these two datapaths has higher throughput? Why? Solution: Datapath throughput is the rate of executing instructions, i.e., it is the number of instructions completed per unit time. (a) Single-cycle datapath throughput = 10-6/T1 MIPS (b) Throughput of n-stage pipeline = 10-6/Tn MIPS (c) Pipelined datapath has a higher throughput, because its cycle time is approximately 1/n of the single-cycle datapath. Problem 3: Consider a single-cycle datapath whose cycle time is T. To reorganize datapath as an n-stage pipeline, the hardware is divided into n nearly equal delay stages. The cycle time for the pipelined datapath is then the largest delay of any stage. Suppose this cycle time is given as (T/n) + n, where >0 is a small constant and n ≥ 2. Find the number of stages that will maximize the throughput for long instruction streams. If T = 10ns and  = 0.1ns, what are the throughputs of the single-cycle, 5-stage pipeline, and the optimum pipeline datapaths? Neglect the effect of latency.