Download Solved Exam 2 for Advanced VLSI Design and Applications | ECEN 6263 and more Exams Electrical and Electronics Engineering in PDF only on Docsity! ECEN 6263
Fall 2003
Exam 2
WRITE YOUR NAME HERE Alun
All questions must be answered on test paper!
Open Book, Open Notes
1. For the following circuit, assume A switches from 0 to 1 and CL=1.
ECEN 6263 Feil 2003 Exem 2 ‘November 13, 2003 1
b. Write the conductance matrix, lal , for nodel, node2 and node3 only in terms of the
channel conductances (not resistances) of the individual transistors.
! L 3
[G6 O -Su
4 O 2G -6,
3 -G ~6;, 6,16,
c. Write the resistance matrix, [Rl = (al 7 , for nodel, node2 and node3 only in terms
of the channel resistances of the individual transistors. Hint: you do not have to
invert the matrix if you already know the answer.
) ] 3
ae ERR Bp ae
2] R;, BAR IR
3 | RP, Rte Ret >
BCEN 6263 Fall 2003 Exam 2 November 13, 2003 2
3. Answer the questions below for the following layout (all dimensions in 4),
source gate
with the following capacitive parameters:
AAGAF4A.@
AO.) Ce)
and the following sheet resistive parameters:
Rae Rip Rip Ron Rp Ry,
Answer the following only for the part of the layout shown above.
a. What is the effective channel width?
Mee Er erkr er trh st |)
W f= 2*20>= 40%
b. What is the channel resistance when the transistor is passing a low signal?
R= Rag BD ~ L
Ws, Pade ae
2u .
ECEN 6263 Fall 2003 Exam 2 November 13, 2063
iq
c. Using the simplified switching model for the transistor in cutoff, what is the capaci-
tance of the gate node that couples to ground?
' Dr
Cg = (psn eur HAD D> tOWDAS »)
+ Eeg\(Zu.2> 4 22-2 gH 2) $4 thew )
tepyp\ (20d 4 1 + 224 ten, EN
= Lon’ t/G ~~ YA 'LO
a. Using the Abas ce site in “a. ne is the capaci-
tance of the gate node that couples to the source node?
=) Cr) Dy -
3 = PT PNP NY, an YW
85 = EY 4s
= fe free *
z (Se ff ZA
e. Using the simplified switching modei for the transistor in cutoff, what is the capaci-
tance of the gate node that couples to the drain node?
(qd: (=) Z>- 4
we
~~
. 2 Couns ov &>
f£ Using the simplified switchisig model for the transistor turned on, what is the capaci-
tance of the gate node that couples to ground?
G= (EP LEI
g. Using the simplified switching model for the transistor turned on, what is the capaci-
tance of the gate node that couples to the source node?
C55 = L Ee) be 4 (2*) y D4
=EX)4P” + bre?) 320
b. Using the simplified switching model for the transistor turned on, what is the capaci-
tance of the gate node that couples to the drain node?
cod 5 (GIF + Cr) | mP
= RY)” + beat) Eo
BOEN 6263 Fell 2003 Exam 2 ‘November 13, 2003
