Solved Questions in Exam 2 - Advanced VLSI Design and Application | ECEN 6263, Exams of Electrical and Electronics Engineering

Download Solved Questions in Exam 2 - Advanced VLSI Design and Application | ECEN 6263 and more Exams Electrical and Electronics Engineering in PDF only on Docsity! ECEN 6263 Fall 2004 Exam 2 WRITE YOUR NAME HERE Ansa ; All questions must be answered on test paper! Open Book, Open Notes 1, The layout below is for a transistor designed with deep submicron design rules which require a 42, spacing between poly lines making smaller doglegs in the poly lines. The dogleg portion (shown in the small box) has an approximate resistance/conductance of 3/4 square. . oO metal 1 a a || contact EE rv gate active source drain a. What is the channel resistance of this transistor? Express your answer in terms of the (iL channel sheet resistance, R,,,, and the grid spacing i. ae (x 6 43, 45 4\920 en 2 4 ZF 2 + B= RRs te tate gto Bs ny’ R= Kos io 20 ECEN 6263 Fall 2004 Exam 2 ‘November 12, 2004 page | of 4 b. Using the parameters (2), (3) ; (<2), (Sa), (Sat) and the grid spac- ing, 2, what is the drain capacitance to ground (neglect gate capacitance)? C42 ey Thx4 + bret Th > ie) (dauy> + Oly aL (74 + [tht] + Th)x2 <5>(od\4b> y+ Os) + Og \416> c. Using the parameters (<4), (=), (<=), (Seize ‘), (Se=2) and the grid spac- ing, 2, what is the source capacitance to ground (neglect gate capacitance)? us Cy = =) (52*8) + YLXIO + % oh <54)x2> “BY (5h + 214 54)x2 4 4 (op \ agers) > J Cs2(S8) 211% + OLE « fa) 46D \ as d. Using the parameters (<3), (=) ; (<4, (Sai=2) , (Ce1=2) and the grid spac- ing, 4, what is the drain to source capacitance (neglect gate capacitance)? Cl.c : ~ ds (IE) te a + ou) > = fmed) Son ECEN 6263 Fall 2004 Exam 2 ‘November 12, 2004 page 2 of 4