VLSI Design: Static Sequential Logic Circuits and Memory Elements - Prof. Aurangzeb Khan, Study notes of Electrical and Electronics Engineering

Download VLSI Design: Static Sequential Logic Circuits and Memory Elements - Prof. Aurangzeb Khan and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! EE 534 fall 2003 University of South Alabama EE534 VLSI Design System Fall 2003 Lecture 19:Chapter 8 Static sequential logic circuits design EE 534 fall 2003 University of South Alabama Sequential Logic circuits The logic circuits considered thus far are called combinational logic circuits. Their output depend only on the present value of input. This implies that these circuit do not have memory. Another class of the logic circuit that incorporate memory are called sequential logic circuits; that is, their output depend not only the present value of the input, but also on the previous history of inputs. Shift registers and flip-flops are typical examples of such circuits. EE 534 fall 2003 University of South Alabama Sequential Logic Combinational Logic OutputsInputs S ta te R eg is te rs Current State Next State clock EE 534 fall 2003 University of South Alabama Latches vs Flipflops Latches level sensitive circuit that passes inputs to Q when the clock is high (or low) - transparent mode input sampled on the falling edge of the clock is held stable when clock is low (or high) - hold mode Flipflops (edge-triggered) edge sensitive circuits that sample the inputs on a clock transition - positive edge-triggered: 0 → 1 - negative edge-triggered: 1 → 0 built using latches (e.g., master-slave flipflops) Flip-flop: not transparent—reading input and changing output are separate events. EE 534 fall 2003 University of South Alabama Memory element parameters Setup time: time before clock during which data input must be stable. Hold time: time after clock event for which data input must remain stable. clock data EE 534 fall 2003 University of South Alabama Latch Layout VDD D Q’ VSS φ’φ EE 534 fall 2003 University of South Alabama CMOS RS Latch Circuit The operation sequence of CMOS R-S Latch is following. For example: If S = logic 1 and R = logic 0, then MN1, is turned on, Mp1, is cut off, and goes low. With = R = logic 0, then both MN3 and MN4 are cut off, both MP3 and Mp4 are biased in a conducting state so that the output Q goes high. With Q = logic 1, MN2 is biased on, Mp2 is biased off, and the flip-flop is in a set condition. When S goes low, MN1, turns off, but MN2 remains conducting, so the state of the flip- flop does not change. Q Q EE 534 fall 2003 University of South Alabama CMOS R-S Latch (cont.) When S = logic 0 and R = logic 1, then output Q is forced low, output goes high, and the flip-flop is in a reset condition. Again, a logic 1 at both S and R is considered to be a forbidden or a nonallowed condition, since the resulting outputs are not complementary. Q EE 534 fall 2003 University of South Alabama SR Latch disallowed0011 reset1010 set0101 memoryQQ00 QQRS S Q Q R EE 534 fall 2003 University of South Alabama SR-Flip Flop (SR FF) characteristic tableNOR based Q 1 0 0 Q 0 1 0 S Q 1 0 1 Q 0 1 1 quiescent state set reset forbidden Later state underterminable if S/R switch simultaneously!! RS Q Q S Q 00QS R Q 01 0 1QR 11 NAND based R Q QS Q QS R Q 11 0 1QR 1 0 00 EE 534 fall 2003 University of South Alabama Other Latches Clocked SR latch Adds clock input. Latch output can only be set/reset when clk=1 (or clk=0) Other latch types: JK latch: Removes “not allowed” state - toggles when inputs are both 1 T latch: Toggles when input = 1 D latch: Output = input EE 534 fall 2003 University of South Alabama Clocked D Latch D Q !Q clock clock D L at ch QD transparent mode clock hold mode EE 534 fall 2003 University of South Alabama MUX Based Latches Change the stored value by cutting the feedback loop clk 0 1 feedback clk 1 0 feedback Q Q D D Negative Latch Positive Latch Q = !clk & Q | clk & DQ = clk & Q | !clk & D transparent when the clock is low transparent when the clock is high EE 534 fall 2003 University of South Alabama TG MUX Based Latch Implementation Q D clk clk !clk !clk clk input sampled (transparent mode) feedback (hold mode) clk D L at ch QD