Digital Integrated Circuit Design Lab: Static Timing Analysis using PrimeTime, Lab Reports of Electrical and Electronics Engineering

Download Digital Integrated Circuit Design Lab: Static Timing Analysis using PrimeTime and more Lab Reports Electrical and Electronics Engineering in PDF only on Docsity! ECEN 454 Digital Integrated Circuit Design Lab11 Static Timing Analysis - PrimeTime 1. Introduction Timing analysis is to check the timing requirement of the circuit. You can do timing analysis in different design levels. In lab9 we use Synopsys Design Compiler to synthesis a design and do timing analysis in gate level after the optimization. In this lab, you will learn to use another Synopsys tool, called PrimeTime, to do timing analysis. PrimeTime is a standard-alone tool and is specified for timing analysis. It is more powerful than Design Compiler in timing areas. Similar to Cadence Silicon Ensemble, PrimeTime can only read in structural level circuits. The synthesized circuit generated using Design Compiler in Lab9 will be used even here. 2.Using PrimeTime 1.Environment Setup We shall use the same directory cru_con/ which we used in the previous lab to perform place and route on the synthesized circuit. Make sure you have the iit018_stdcells.db and iit018_stdcells.lib files in the same folder. If not download the same from the lab website. The iit018_stdcells.db is the timing library file in Synopsys format and iit018_stdcells.lib is the same timing library file in ASCII format. Browse through the iit018_stdcells.lib file and you will find the timing information of each standard cell in table format. If not specified, PrimeTime uses these tables to compute gate delays in the circuit. You may modify these tables according to your own simulation (SPICE?), and use "lc_shell" (Library Compiler shell) to compile the text file to db file. 2.Circuit Make sure you have the synthesized verilog netlist in the same folder.(You must have it since you used it to perform Place and Route as well). Also check if you have generated the SPEF file from Encounter after completion of Place and Route. This file will be used to consider layout information in timing analysis. 3.Read Libraries Type "primetime &" in your terminal, then the primetime console window appears. If you can't find this command, try to add "source /usr/local/bin/setup.synopsys" into file ".cshrc" at your home directory, then open a new terminal. In the console window, click "File -> Search and Link Path". In the pop-up window, type "." in column "Search Path" and type "* iit018_stdcells.db" (there is a space between the * and the library name) in column "Link Path", then click "OK". This is to indicate PrimeTime that the running library is to be found in the current directory. Please note in primetime console window you will see the corresponding messages about what you did. Note if there appears message in red color, normally you have operation errors. 4.Setup Design Click "File-->Open" to read in your circuit design. Please select files of type as "verilog" then you will see the verilog file, highlight your file and click "OK". Dismiss the pop-up window. Then click "Design -->Current" and choose top module in your design. Click "OK" then. Next step is to link the design to the running library. You can do this by clicking "Design --> Link" and choose your top module to link. 5.Set Capacitance for output ports The output ports of your design are to be connected to other blocks. Therefore you need to set the driving capacitance for them. Click "Attributes --> Capacitance -->Set Port/Net Capacitance" then the set capacitance window pops up. You can click button "Browse..." to select output ports and set the max value to be 3. 6.Set driving strength for input ports You need to provide driving strength to the input ports of your design. You may do it by clicking "Attributes --> Port Drive --> Set Driving Cell...". Then use the "Browse" button to choose the input ports and choose cell "BUFX2" as the driving cell. Then click "Ok". 7.Set Clock Details To set the time period for the clock choose "Attributes --> Clock --> Create" . Use Browse to choose the clock source pin in your design. and set the period of the clock to 10. 8.After setting the clock details we intend to perform a check_timing command before we begin the timing analysis. The check_timing command shows possible timing problems for the design. To type in the command use the space at the bottom of the console. You may type in the command next to the space after "primetime>" . After the command is executed you will see there are a few warnings that may appear on the console window. The warnings may say There are * ports with no clock-relative input delay specified and There are * endpoints which are not constrained for maximum delay. This is because we have not specified the required arrival time for the signals at the input and output pins relative to the clock signal. 9.To specify the arrival time for the input signals relative to the clock choose "Attributes-->Port Delay-->Input". Use Browse again to choose all the input pins and the Maximum Rise and Minimum Rise delay as 0 and ensure that the Reference Clock refers to the name of the clock symbol in your design. 10.To specify the arrival time for the output signals relative to the clock choose "Attributes-->Port Delay-->Output". Use Browse to select all the output pins type in 5 for the Maximum Rise and Minimum Rise times and also ensure that the Reference Clock refers to the name of the clock symbol in your design. 11. Now execute the check_timing command again and you must be able to get a clean output on the console window. 12.Next we check if there is are any setup time violations on any of the cells in the circuit. We do this by typing in the follwoing command