Substrate - Microelectronic Devices and Circuits - Solved Exam, Exams of Microelectronic Circuits

Download Substrate - Microelectronic Devices and Circuits - Solved Exam and more Exams Microelectronic Circuits in PDF only on Docsity! UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Professor Oldham Spring 1999 EECS 105 — Midterm 1 Thursday, 25 February 1999 Your name: first last Your discussion TA: (© Allan Chang O Lily Tam « This is a closed book exam, but you may use your page of notes. ¢ Please do all your work on the pages of this exam. Ask if you need extra paper. * Full credit will be given only when you indicate the source of your answer, such as a table, graph, or calcala- tion. ¢ Please write your name in the above space ¢ Special notes: 41. SOME GRAPHS AND FORMULAS ARE GIVEN AS APPENDICES TO THIS EXAM. BE SURE TO LOOK THESE OVER. Yes, I have looked these over. (Check box) 2. SOME PARTS OF THE EXAM ARE GRADED WITH NO PARTIAL CREDIT. They are noted. You may wish to double check your answers on those parts. 3. ONCE IN A WHILE SOME EXTRA CREDIT IS POSSIBLE FOR CLEVER INSIGHT. Again, these places are noted. But we will not answer questions about these problems. Just be very clear in your work. SCORE Problem 1 (20 pts.) Problem 2 (25 pts.) Problem 3 (30 pts.) Problem 4 (25 pts.) TOTAL (100 pts.) Problem 1 (20 pts.) a. [No partial credit] In a certain process, a 2m thick layer of n-type silicon (doping = 2 x 1015/em? is created over a p-type substrate. It is to be used for the purpose of making integrated circuit resistors. What is the sheet resistance of this (Units must be Q/: eS L Ry ~ ae “ jéank LY O” ¥ (Fron Por ~BS0) =1L6kJL b. Using the layers of (a), above, you need to make a resistor with value of 200K. It is Sum wide. What must its length be (ignoring contact effects)? ~{ RY) Re Lk. Ree 7 Ww We kK =/9,25 W L= KILLS 26 wm c. Someone properly points out to you that the layer in part a), though it is physically 2j1m thick, is electri- cally somewhat thinner, because there must be a depletion layer at the n-p interface. (You are to ignore this in part a.) Suppose the doping in the p region is also 2x 1015/cm” (but acceptors instead of donors). At zero applied voltage between the n and p regions (i.e., in thermal equilibrium), just what is the net electrical thickness of the n-region? (Thickness minus depleted portion.) 26V <—— - ,32V Kg | Bie b./2 C because. re JNA SYnMeErtic \ = 0.45 um a = O45 um) 1ofé d. Now we adjust the flat-band voltage (and thus the threshold voltage) with an ion implant just at the bottom of the gate oxide. We set the implant value to get a final threshold V;, of 0.5 V. In testing the device we short source to body, ie., Vez = 0. d.1) [No partial credit] What is Vpo4y of this device if we set Vg, = 2 V? Vosar > Ves-U, = 1 SV LSU d.2) Neatly sketch the I-V characteristics on the linear axes below for three cases: Ves = 0.5 V, Ves = 1V, and Vgs = 2 V. Cover the range Vps = 0 to 5 V. Assume the electron mobility in the channel is 500 em?/ Vsec. You must put a scale on the current axis, (Note that partial credit will only be possible if you very carefully show your work, including giving any formulas you are using before evaluation.) y 13 ~S Losar (w= Coy “4 t (Ves- y) = 7407 %.O7rK Yr $0. # “$600? ty yt -¥~ Tsar (rv) = Dysar (iv) a(t) > GAXK/0" 7 6 %mA Nob uk Vosyr Dy 2 Fer 7S Drain Current vs VDS wf Vacrr Ly = Dart 2, —# (6 & Drain Current (mf) 'e~ 2 Drain-Source Voltage Vye7? Goofs Problem 4 (25 points) A p-n junction capacitor is made in an integrated circuit with the cross-section as shown below. The p-region is very heavily doped compared to the n-region (it is a p*n junction) and the n-region doping is 1 x 1014/ cm’. The junction area is 100 x 200m, or 2 x 104 om’, ntype a———metal contact ww) G2 -.ss (see hrs, pcan topside Qn= cox > a4 we x=O i | _-—metal contact to Oe. ~ 174 nside wy a) Make a sketch of the charge density p (C/cm?), the electric field E (V/cm), and the potential @ versus x for this structure at 5V reverse bias. The “graph paper” is provided on the page opposite. As part of the calcula- tion to prepare these graphs, please compute the following: a.1) The built in voltage a.2) The depletion width at 5V reverse bias fare 2€ (Mar +5) = 7H a.3) The peak electric field at 5V reverse bias Q Zo Kd —_— — Eg F.gsxiote iG b) What is the small-signal capacitance at SV reverse bias? Formula (in terms of known quantities) Value Tots O ‘1G (Vv) 3%. 65" (um) 3 13.3 X10" wiem) Aés/X{F 0,239 pF  P 4 — = 1.60" 0 mo x Xa E A 9 eX — 13,3 K10* Yom ® A #24 bo... —_— 4 0 ——/-65 c) The n-region ends in an ohmic contact at x = 15um. Taking into account the answer to part a.2, calculate the current at 0.7V forward bias. But We= IS —~ Xe (0. Iv Fw Sas] ¢.1) First give the ula Wenyh in terms of doping, geometry, etc. (All must be known quantities.) L= Aig Dp Boe MW, . =< , ¢.2) LiXt the val of alr ttiesi mula above 7 1.06 6 or Kot 2x04 berg lt eK500 !O%C _(S=Xq X10 ¢.3) Evaluate the current X_r (2079-2) 2 LOG hu ONS _ ois le /50, 09048 Bof8