Syatem Mapping-Data Communication Network-Lecture Slides, Slides of Data Communication Systems and Computer Networks

Download Syatem Mapping-Data Communication Network-Lecture Slides and more Slides Data Communication Systems and Computer Networks in PDF only on Docsity! SS-CARE School of Engineering Spring 2007 HDL Based Digital Design CE3204 Lecture 10-11 Design with Memories HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering oT “Oy Verifiable Subset =m There are two ways of constructing a design: one way is to make it so s/mp/e that there are obviously no deficiencies, the other is to make it so complicated that there are no obvious deficiencies. Verifiable Subset Principle A design project must select a simple HDL verifiable subset, to serve all verification tools and to provide an uncomplicated mechanism to convey clear functional intent. HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering Verifiable Verilog Keyword s The verifiable subset is the subset of the synthesizable one m Only 23 Verilog-1995 keywords are selected always begin case casez default else end endcase endfunction endmodule _ for function if inout input module negedge or output parameter posedge reg wire The use of keywords is minimized HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering 6 Asynchronous logic = Asynchronous principle = A design must minimize and isolate resynchronization logic between asynchronous clock domains = Asynchronous design = Not cycle-by-cycle fashion = Cannot be addressed at RTL abstraction HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering 7 Verilog Testbench = A testbench facilitates verification of a design or module by providing test vectors and comparing the response to the expected response = The design (top- level module) or (lower- level) module is instantiated inside the testbench, and behavioral statements are used to apply test vectors and evaluate the response = Constructs that are not synthesizable can be used HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering 10 Systems and Their Mapping Throughput Requirement @ bd bilbl..! bn in[0] in{1] in[2] . in[3] in[0] in[{1] in[2] in[3] ... wes automotive few Hz speech 8kHz 12-16 bits audio 44.1kHz 16-24 bits video 13.5 MHz _ 8-12 bits HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering 12 One to One Mapping input_a || imput_b input_c |] input_d ) oy ! multiplier_! subtractor / multiplier_2 | output_x HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering 15 What if it is Too Slow?? =» How can we make it run faster? Pipeline it HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering 16 Pipelining in one-to-one mappin OBO -+@) allocation A B Cc D assignment | A > B > C >» D — >, Analyze timing pipelining | A +> B HH Cc HH D * if OK then stop * else pipelining +-=— ff |-> f clock clocked flipflop HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering 17 Pipelining and Time Shared Architecture z 2 Bs ATEN Pipelining Before Pipelining I/P O/P Combinational Cloud HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering 21 $5, S Bs FTN S ie ‘an Pipelining VP O/P After Pipelining Combinational Register 2 Combinational Cloud 1 Register 1 —___4 Combinational Cloud 2 HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering 22 Initial Architecture out HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering 25 Pipeline Architecture out HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering 26 We can achieve speed by pipelini Pipeline Stage Pipeline introduction Stage a[S] b[S] al4]bI4] 5 al2] b[2] a1] b[1 ud F& |leal FA |les} FA | col Fa Jlea| FA | co] FA cos cos cs cs c os cos ei Sl sta SI SI] SH] S(O] HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering introduction 27 Align Data / Balance Paths Good discipline to line up pipe stages in diagrams. FA FA Q Gout | FA +4 FA HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering 30 Three Stage Pipelining | | || ai«| F.A Register | Register Register | | | | Register Register Register | A | A | A—___ F.A Register, F.A Reset F.A <i - [ Resister, }—| egis ot | Register I l | Register Register a—_—__. | Register | = Register | Register | A Register | A HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering 31