Synchronization in Parallel Architecture-Advance Computer Architecture-Lecture Slides, Slides of Advanced Computer Architecture

Download Synchronization in Parallel Architecture-Advance Computer Architecture-Lecture Slides and more Slides Advanced Computer Architecture in PDF only on Docsity! Today’s Topics Recap: Performance of Multiprocessors with – Symmetric Shared-Memory – Distributed Shared Memory Synchronization in Parallel Architecture Conclusion docsity.com Recap: Cache Coherence Problem So far we have discussed the sharing of caches for multi-processing in the:  symmetric shared-memory architecture  Distributed shared memory architecture We have studied cache coherence problem in symmetric and distributed shared- memory multiprocessors; and have noticed that this problem is indeed performance- critical docsity.com Recap: Implementation Complications of snoopy protocols The three states of the basic FSM are: Shared, Exclusive or Invalid However, the complications such as: write races, interventions and invalidation have been observed in the implementation of snoopy protocols; and to overcome these complications number of variations in the FSM controller have been suggested These variations are: MESI Protocol, Barkley Protocol and Illinois Protocol docsity.com Recap: Variations in snoopy protocols These variations resulted in four (4) states FSM controller –The states of MESI Protocol are: Modify, Exclusive, Shared and Invalid –The sates of Barkley Protocol are: Owned- Exclusive, Owned-Sheared, Shared and Invalid; and of – Illinois Protocol are: Private Dirty, Private clean, shared and Invalid docsity.com Recap: Directory based Protocols The larger multiprocessor systems employ distributed shared-memory , i.e., a separate memory per processor is provided Here, the Cache Coherency is achieved using non-cached pages or directory containing information for every block in memory The directory-based protocol tracks state of every block in every cache and finds the ….. docsity.com Recap: Directory Based Protocols These protocols involve three processors or nodes, namely: local, home and remote nodes – Local node originates the request – Home node stores the memory location of an address – Remote node holds a copy of a cache block, whether exclusive or shared docsity.com Recap: Directory-based Protocol The transactions are caused by the messages such as: read misses, write misses, invalidates or data fetch requests These messages are sent to the directory to cause actions such as: update directory state and to satisfy requests The controller tracks all copies of memory block; and indicates an action that updates the sharing set docsity.com Example: Working of Finite State Machine Controller Now are going to discuss the state transition and messages generated by FSM controller in each state to implement the directory-based protocols. We consider an example distributed shared- memory multiprocessor having two processors P1 and P2 where each processor has its own cache, memory and directory docsity.com Example: Working of Finite State Machine Controller Let us assume that the initially the cache states are Uncached (i.e., the block of data is in memory); and at the first step P1 write 10 to address A1, here the following three activities take place 1.The bus action is write miss and the processor P1 places the address A1 on the bus; 2. the data value reply message is sent to the controller, P1 is inserted in the directory sharer-set {P1}; and docsity.com Example: Working of Finite State Machine Controller 3. the state transition from Uncached to exclusive takes place – these operations are shown here in red color P1 P2 Bus Directory Memory step State Addr ValueState Addr ValueAction Proc. Addr Value Addr State {Procs} Value P1: Write 10 to A1 WrMs P1 A1 A1 Ex {P1} Excl. A1 10 DaRp P1 A1 0 P1: Read A1 P2: Read A1 P2: Write 40 to A22: Write 20 to A1 Processor 1 Processor 2 Interconnect Memory Directory docsity.com Example: Working of Finite State Machine Controller At Step 2 – P1 reads A1; CPU read HITs occurs, hence the FSM Stays in exclusive state P1 P2 Bus Directory Memory step State Addr ValueState Addr ValueAction Proc. Addr Value Addr State {Procs} Value P1: Write 10 to A1 WrMs P1 A1 A1 Ex {P1} Excl. A1 10 DaRp P1 A1 0 P1: Read A1 Excl. A1 10 P2: Read A1 P2: Write 40 to A2 P2: Write 20 to A1 Processor 1 Processor 2 Interconnect Mem Directory docsity.com