Download Synchronous Sequential Logic: Understanding Flip-Flops and Latches - Prof. Costa P. Gerous and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! 1 Synchronous Sequential Logic A digital system has combinational logic as well as sequential logic. The latter includes storage elements. feedback path § The binary information stored in the memory elements at any given time defines the state of the sequential circuit at that time. § The sequential circuit receives binary information from the external inputs. These inputs together with the present state of the storage elements, determine the binary value of the outputs. Synchronous Sequential Logic § A synchronous sequential circuit employs signal that affect the storage elements only at discrete instants of time. § Synchronization is achieved by a time device called ______ that provides a periodic train of ______. § Storage elements that are used in clocked sequential circuits are called ______. § A ______ is a a binary storage device capable of storing one bit of information. flip-flops clock pulses flip-flop 2 Synchronous Clocked Sequential Logic LATCHES The most basic types of flip-flops are the latches that operate with signal levels. Latches are the building blocks of all flip-flops. Under normal conditions, both inputs of the latch remain 0 unless the state has to be changed. When S = 1à latch to ‘set’ state: Q = 1, Q’ = 0. Before R is reset to 1, S must go back to 0 to avoid the occurrence of an undefined state with both outputs = 0 undefined state 5 Edge-Triggered Flip-Flop The circuit samples the D input and changes its output at the negative edge of the clock, CLK . When the clock is 0, the output of the inverter is 1. The slave latch is enabled and its output Q is equal to the master output Y. The master latch is disabled (CLK = 0). When the CLK changes to high, D input is transferred to the master latch. The slave remains disabled as long as C is low. Any change in the input changes Y, but not Q. à The output of the flip-flop can change when CLK makes a transition 1à 0 Positive-Edge-Triggered Flip-Flop • If D = 0 when CLK Rà 0, Q = 0: ‘reset state’ • If D changes while CLK is high à flip-flop will not respond to the change. •When CLK , R à1, flip-flop will be in the same state (no change in output). •If D = 1 when CLK , Sà 0, Q = 1: ‘set state’ 6 Edge-Triggered Flip-Flop: Graphic Symbols The most economical and efficient flip-flop constructed is the edge-triggered D flip-flop since it requires the smallest number of gates. JK Flip-Flop QKJQD ''+= When J = 1 and K = 0, D = 1à next clock edge sets output to 1. When J = 0 and K = 1, D = 0à next clock edge resets output to 0. When J = 1 and K = 1, D = Q’à next clock edge complements output. When J = 0 and K = 0, D = Qà next clock edge leaves output unchanged. Compare the number of logic devices in the JK and D flip-flop.
