Download FSM Synthesis Tips and Examples and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! 1 1 ECE 4514 Synthesis of Finite State Machines Martin 2003ECE 4514 2 Last time Xilinx/Synplicity synthesis hints • Grouping/ordering operands • Case/If: Priority logic • Block RAM inference. (Xilinx manual is wrong…) • Resource sharing Today: FSM hints from Synplify manual. Martin 2003ECE 4514 3 Finite State Machines Synplify only handles synchronous sequential hardware • No asynchronous seq'l machines • Must have a clock • Warning about "combinational loop" output <= (((((g and d) or (not g)) and output) or d) or not output); Martin 2003ECE 4514 4 Finite State Machines Right way: output1 <= (((((g and d) or (not g)) and output_r) or d) or not output_r); Process (clk, reset) begin if reset = '0' then output_r <= '0'; elsif clk'event and clk='1' then output_r <= output1; end if; end process; Martin 2003ECE 4514 5 Finite State Machines Martin 2003ECE 4514 6 FSM hints Use enumerated types to represent states • Don't hardwire state assignments in a vector. Example: Type states is (state0, state1, state2); Signal current_state: states; If current_state = state0 then… Not: signal current_state: std_logic_vector(2 downto 0); If current_state = "000" then… 2 Martin 2003ECE 4514 7 FSM hints Use two processes: • Combinational next state/output logic in one process, sequential logic in another. Example: Process(clk, reset) Begin if reset = '0' then current_state <= state0; elsif (clk'event and clk='1') then current_state <= next_state; end if; End process; Process(current_state, in1) Begin case current_state is when state0 => if in1 = '1' then next_state <= state1; out1 <='1'; end if; when state1 => … Martin 2003ECE 4514 8 FSM hints Assign default values to signals before the case/if statement • Usually easier to read, especially for ouputs that are used only be a few states. • Avoids inadvertent latches… Example: Process(current_state, in1) Begin out1 <= '0'; next_state <= current_state; case current_state is when state0 => if in1 = '1' then next_state <= state1; out1 <='1'; end if; when state1 => … Martin 2003ECE 4514 9 FSM example Process(current_state, in1) --other process not shown Begin --see previous slides out1 <= '0'; -- Default values for out1 next_state <= current_state; -- and next_state… case current_state is when state0 => if in1 = '1' then next_state <= state1; out1 <='1'; end if; when state1 => if in1 = '1' then next_state <= state2; out1 <= '1'; end if; when state2 => if in1 = '0' then next_state <= state1; else next_state <= state0; end if; end case; end process; Martin 2003ECE 4514 10 Example 3 LUTs Martin 2003ECE 4514 11 Example 5 LUTs without default assignment to next_state Martin 2003ECE 4514 12 A problem Create a state machine to control an ALU to find the average of 2 numbers. The first number will be available on the first rising clock edge after GO is asserted, and then the next number on the clock cycle after that. GO will only be high for one cycle. Reset is asynchronous, active high. FIN should be raised when the output is valid. The output should remain valid until GO is asserted again. The ALU implements 4 operations ( < 1 cycle ) : • 00: Add A and B • 01: Shift A right one bit • 10: Pass through B • 11: Pass through A
