Systems - Computer Science - Lecture Slides, Slides of Computer Science

Download Systems - Computer Science - Lecture Slides and more Slides Computer Science in PDF only on Docsity! RTL Systems Docsity.com Introduction 1. DATA SUBSYSTEM (datapath) AND CONTROL SUBSYSTEM 2. THE STATE OF DATA SUBSYSTEM: – CONTENTS OF A SET OF REGISTERS 3. THE FUNCTION OF THE SYSTEM PERFORMED AS A SEQUENCE OF REGISTER TRANSFERS (in one or more clock cycles) 4. A REGISTER TRANSFER: – A TRANSFORMATION PERFORMED ON A DATA Docsity.com CENTRALIZED CONTROL BATA GoW M UMICATICHR Cala Control signak CT MODULE 4 }_—______= Condiions a MOOULE 2 E SS MODULE 3 te 4 Docsity.com DeCENTRALIZED CONTROL CATA, COM Ma od Dists 2 KDILILE 7 —<$<$<$< i MWODLILE 2 J——<—<$_< iODLILE 2 Sequencing contra signa Docsity.com SemiCENTRALIZED CONTROL CATA, id MU TO Conia na MOCGULE 1 dgmais | MOCGULE 2 Condljcans CONTROL — MOCULE = | te “s., Mod uke contol Docsity.com Analysis of a RTL system (cont) PROCESS (clk) BEGIN IF (clk = *i') THEN CASE state If WHEN S0 => atate <= é WHEN é WHEN Sk => atate <= : END CASE; END IF; END PROCESS ; PROCESS (state,ctrl_in} BEGIN CASE state I5 WHEN 50 => data_ctrls <= WHEN WHEN Sk => data_ctrls <= END CASE; END PROCESS; END general; -- contrel subaystem, —------------— + -- transition function -- Transitions might depend on -- data conditions, described by -- IF statemente in each state -- contrel subsystem, -- output function ; ctrl_lout <= : ctrl_out <= i Docsity.com Design of Data Subsystem 1. Determine the operators (functional units) -Two operations can be assigned to the same functional unit if they form part of diff erent groups 2. Determine the registers required to store operands, results, and intermediate variables -Two variables can be assigned to the same register if they are active in disjoint time intervals Docsity.com Design of Data Subsystem (cont) 3. Connect the components by datapaths (wires and multiplexers) as required by the transfers in the sequence 4. DETERMINE THE CONTROL SIGNALS AND CONDITIONS required by the sequence 5. DESCRIBE THE STRUCTURE OF THE DATA SECTION by a logic diagram, a net list, or a VHDL structural description Docsity.com WA RAI Register File ‘fo kK OS -—° Wr Kk Register k oS File t= RAP clk of fn #l #I Figure 14.2: REGISTER FILE Docsity.com Entity Declaration of Register File ENTITY reg_file IS GENERIC(n: NATURAL:=16; -- word width p: NATURAL:= 8; -- register file size k: NATURAL:= 3); -- bits in address vector PORT (X : IN UNSIGNED(n-1 DOWNTO 0); -- input WA : IN UNSIGNED(k-1 DOWNTO 0); -- write address RAl : IN UNSIGNED(k-1 DOWNTO 0); -- read address (left) RAr : IN UNSIGNED(k-1 DOWNTO 0); -- read address (right) Zl,Zr: OUT UNSIGNED(n-1 DOWNTO 0); -- output (left,right) Wr : IN BIT; -- write control signal clk : IN BIT); -- clock END reg_file; Docsity.com Behavioral Description of Register File ARCHITECTURE behavioral OF reg_file IS SUBTYPE WordT IS UNSIGNED(n-1 DOWNTO 0); TYPE StorageT IS ARRAY(0 TO p-1) OF WordT; SIGNAL RF: StorageT; -- reg. file contents BEGIN PROCESS (clk) -- state transition BEGIN IF (clk'EVENT AND clk = '1') AND (Wr = '1') THEN RF(CONV_INTEGER(WA)) <= X; -- write operation END IF; END PROCESS; PROCESS (RAl,RAr,RF) BEGIN -- output function Zl <= RF(CONV_INTEGER(RAl)); Zr <= RF(CONV_INTEGER(RAr)); END PROCESS; END behavioral; Docsity.com RAM Description ARCHITECTURE behavioral OF ram IS SUBTYPE WordT IS UNSIGNED(n-1 DOWNTO 0); TYPE StorageT IS ARRAY(0 TO p-1) OF WordT; SIGNAL Memory: StorageT; -- RAM state BEGIN PROCESS (Clk) -- state transition BEGIN IF (Clk'EVENT AND Clk = '1') AND (Wr = '1') THEN Memory(CONV_INTEGER(A)) <= X; -- write operation END IF; END PROCESS; PROCESS (Rd,Memory) -- output function BEGIN IF (Rd = '1') THEN -- read operation Z <= Memory(CONV_INTEGER(A)); END IF; END PROCESS; END behavioral; Docsity.com Functional Modules Inputs x_In | \"" Operation selection op_sel < OPERATOR | zZ_out Output Figure 14.4: OPERATOR Docsity.com Data Path • WIDTH OF DATAPATH • PARALLEL OR SERIAL • UNIDIRECTIONAL OR BIDIRECTIONAL • DEDICATED OR SHARED (bus) • DIRECT OR INDIRECT Docsity.com Interface between Data and control sub system ENTITY group_seq_system IS PORT (data_in : IN BIT_VECTOR; -- input data data_out: OUT BIT_VECTOR; -- output data ctrl_in : IN BIT_VECTOR; -- input conditions ctrl_out: OUT BIT_VECTOR; -- output conditions clk : IN BIT 5 END group_seq_system; ARCHITECTURE generalized OF group_seg_system IS SIGNAL controls : BIT_VECTOR; -- control signals -- to data subsystem SIGNAL cends : BIT_VECTOR; -- condition signals -- from data subsystem BEGIN Ui: ENTITY data_subsysten PORT MAP (data_in,data_out,controls,conds,clk); U2: ENTITY control_subsystem PORT MAP (ctrl_in,ctrl_out,conds,controls,clk); END generalized; Docsity.com Design of control sub system 1. DETERMINE THE REGISTER- TRANSFER SEQUENCE 2. ASSIGN ONE STATE TO EACH RT- group 3. DETERMINE STATE-TRANSITION AND OUTPUT FUNCTIONS 4. IMPLEMENT THE CORRESPONDING SEQUENTIAL SYSTEM Docsity.com CONTROL SUBSYSTEM • INPUTS: control inputs to the system and conditions from the data subsystem • OUTPUTS: control signals • ONE STATE PER STATEMENT IN REGISTER-TRANSFER SEQUENCE • TRANSITION FUNCTION CORRESPONDS TO SEQUENCING • OUTPUT FOR EACH STATE CORRESPONDS TO • CONTROL SIGNALS Docsity.com Design of Multiplier (example) Idx oy IdY yn oT ldZ Data shY Control —_—___——__ subsystem subsystem clrZ xin zp starl — clk > clk ——» * done Figure 13.26: MULTIPLIER SCHEME ® Docsity.com Entity Declaration of Multiplier ENTITY multiplier IS GENERIC(n : NATURAL:= 16); -- number of bits in operands PORT (start : IN BIT ; xin,yin: IN UNSIGNED(n-1 DOWNTO 0); clk : IN BIT ; zout : OUT UNSIGNED(2*n-1 DOWNTO 0); done : OUT bit); END multiplier; ® Docsity.com Control system of Multiplier done = 1 controls = 00000 controls =(IdX,Id¥,ldZ,sh¥’,clrZ) done = 0 controls = 11001 controls =00110 controls = 00110 controls = 00110 Figure 13.27: STATE DIAGRAM FOR MULTIPLIER CONTROL SUBSYSTEM. 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