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Temperature Increases - Microelectronic Devices and Circuits - Solved Exam, Exams of Microelectronic Circuits

Main points of this past exam are: Temperature Increases, Qualitative Explanation, Concentration of Holes, Electrons and Positive, Room Temperature, Gnegative Ions, Doped

Typology: Exams

2012/2013

Uploaded on 03/22/2013

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raghav 🇮🇳

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Download Temperature Increases - Microelectronic Devices and Circuits - Solved Exam and more Exams Microelectronic Circuits in PDF only on Docsity! EECSIOS 1 of7 Fall 1999 Microelectronic Devices and Circuits- EECS105 First Midterm Exam Wednesday, October 6, 1999 Costas J. Spanos University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences Your Name: oss tered So Lytios (last) (first) Your Signature: ia ben ee 1, Print and sign your name on this page before you start. 2. You are allowed a single, handwritten sheet with formulas. No books or notes! 3. Do everything on this exam, and make your methods as clear as possible. Problem 1 /35 Problem 2 IBRSO & bows polars! Problem 3 /25 TOTAL / BC hh10 EECS105 20f7 Fall 1999 Problem 1 of 3. Answer each question briefly and clearly. (35 points) What happens to n; if the temperature increases? Give a brief qualitative explanation (Spts) increases, yecause % themol yeuerarion vt bebe aad obeitrons What is the concentration of holes, electrons and positive/gnegative ions if Si is doped with i917 Boron atoms/cm’, and 10!° As atoms/cm? at room temperature? (nj = 10!)(5pts) we hore Joi 10” eheitrons fern? z WAgld = 10 holes /tvs3 wlo" neyathe Baron sons fom ~ jo"? posite As Fons Am} What are the three types of charges in an MOS capacitor under inversion? Mention carrier type (holes or electrons), ion polarity (positive or negative), charge nature (depletion, accumulation or inversion) and location (gate, substrate surface or bulk). (Gate is n+, bulk is p)/(6pts) in gore: posttrie lous, (depletion) in thanneb: fee eberrrous (inversion) in bul. negarice fous (epfer/on) Find the resistance of the following structure (drawn to scale), if the Rs; (diffusion) is 20 Q/square, Rs» (metal) is 1 O/square and contact hole conductivity (i.e. the area where the two layers touch) is 1Siemens/um?. (Siemens = 1/Q) Assume that “dogbone” contact areas amount to 0.65 squares. (6pts} I I 4 i 1 1» X Lag Diffusion Metal if LILLLE LL, ta Diffusion/Metal A Ry Overlap ey) 9-2 Diffusion/Metal Contact metal H oS Ds 4065406541233 mereP resistame 33x 42/u> 332 diSjuston HS ES: 640.6540.65 < 7.3 oitluston 7esistaare 7.1% 202/146 2 Ceutact pesitoare ee T07AL [Ae EECSIOS 5 of 7 Fall 1999 After the transistor has been completed, apply Vps=0V, Vgg=0V, and Vag = Vino to bring this device to the onset of inversion. Draw 6(x) (with reference to intrinsic silicon) and mark the values of Ving, X gman: (E¢=8-85x10"4F/em, £9,=3.969, &= 11.769, electron charge is -1.6x10°’Cb) (10 points). 40x) + HV Oni y Otpm 62pm 03pm ~Fox| 058 av f Cer Xdwoy2 0-104 pr WN (Tox not drawn to scale) Venu Vie 24% +7, Yonesdlalp) Gat fp lox ossy -o4ny box -3% 2 2 Vino 2 -0.97+ 084 + 166410 Chhe™ p soy 130.0-10 ?F/im* BL Jz 0,0 Poon 20 8104 nm Xue = Apply Vag = 0V, Vps = 2V. Vgg=3V and draw $(x) at a spot very close to the source, and also at a spot very close to the drain. Draw both plots on the same graph, but mark each plot carefully. (Hint: the bulk potential stays the same, at $, with reference to intrinsic silicon in both cases)(/5 points). 7 35 (Yost at) Yar 3 (x) wy WV Bi aave (vost “#) Ww ! _ gtr) cbast tO drein ~yle) Chose to Sound \ ham O.2um 0.3m +V ~Tox| Os x ofiv Havt ¢t Xdyen, “teens = 0.1m Lav “On (Tox not drawn t 0 scale) Sine Vos & Vos-Ven, The t70astitor 1 1A trod é. The plot o§ lx) close to rhe soune books abmon Cihe the abane phot, except for the yare aad oxide potpariind. The plot vl pix) hoe to rhe daly has @ Wyher thanwel pottanal, and as a routy 4 obeper depierion. The yare prrPuilol ond rhe why portatlal of rhese two plots 1 rhe Same. The new dopberion depth i's: Xdnom = |/ 2 £. (. 2 0)%) / a 2¥p +Vbs) peo EECSIOS 6 of 7 Fall 1999 Consider the small signal model for this transistor at Vgg=2V, Vgg=OV. The large signal source Vcc is such that the transistor is saturated. Calculate the values of g, and r, (assume bp=215em?V"!s"1, and that the channel-length modulation parameter A, is 0.1V"1). If we connect a small-signal source vg, = imV, what is the small signal voltage, vgy,, across Ry = 100KQ con- nected as shown? (Do not take to account when you calculate »- (15 points) 30 x Went \ 6 D t $ Vas Vis | m= Epo lox (Vos-Vin) = 4 215 Co V"'S'230 10°F cmd? (.2-0598)V = 696.10 Slomeus -1l. w . too oi Tart tas, ig tet. fo. oy. ge bs (2) Cox (Ve You )y = 5 21 om YS" T50 feo Loos) als Le 27 I: 204K? - - 3 Vout = ~( Pete) Imths= ~ 6718 10° 696-10 OV 2-467 -10 V lout = r/le Yew 6713 KE ie. phere ts abwest @ -5X ah) Siation EECS105 Problem 3 of 3 (25 points) Fall 1999 Consider a short pn junction with I, = 10°A. You want to make a thermometer out of this diode, by feeding it with a constant forward current of 10°3A, and by reading the bias voltage. What kind of function of temperature will be this voltage? (linear or some other kind?) Calculate the Vp val- ues for 0°C, 25°C and 100°C. Graph the relationship between temperature and Vp. (Boltzman’s constant is 1.38 10°23 J/K. The absolute zero temperature is at 0°K or at -273°C.) (75 points) Vb mV 450 400 390 300 vb Tp: Ip @ vr Vile v 2 bb. vod» = HL gy Be aba Be gee gy Laws 3.8) + wis dear Tima Wy, that Vp is 0 Haeas - fusstlon 05 temp. Temperature (°C) How would a npn BIT be affected by the following parameters (draw up or down arrows to indi- cate that a parameter increases or decreases, respectively, given an increase of the respective design variable.) (0 points) Design Variable Be Op Emitter Doping S 4 Emitter Width 4 t Base Doping y v Base Width J v Ge = 1-Of Of purines dopieuy onary hole injection hate eavittor enitter vildth bowers hole dihasron tu Tien bone doping Coners ebbrtion injection ‘aro base base wath Loners elation diffu ston turnt Ze when &¢ improves, 50 oes Of
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