Docsity
Docsity

Prepare for your exams
Prepare for your exams

Study with the several resources on Docsity


Earn points to download
Earn points to download

Earn points by helping other students or get them with a premium plan


Guidelines and tips
Guidelines and tips

Test 2 ch.8 | C S 3113 - Introduction to Operating Systems, Quizzes of Computer Science

Flash card for Ch.8 Class: C S 3113 - Introduction to Operating Systems; Subject: COMPUTER SCIENCE; University: University of Oklahoma; Term: Fall 2009;

Typology: Quizzes

Pre 2010

Uploaded on 11/09/2009

ebranecky
ebranecky 🇺🇸

16 documents

1 / 10

Toggle sidebar

Partial preview of the text

Download Test 2 ch.8 | C S 3113 - Introduction to Operating Systems and more Quizzes Computer Science in PDF only on Docsity! TERM 1 Base Register DEFINITION 1 holds the smallest legal physical memory address TERM 2 Limit Register DEFINITION 2 specifies the size of the range TERM 3 input queue DEFINITION 3 In computer science, an input queue is a collection of processes in storage that are waiting to be brought into memory to run a program. TERM 4 logical address DEFINITION 4 In computing, a logical address is the address at which an item (memory cell, storage element, network host) appears to reside from the perspective of an executing application program. (address generated by the CPU) TERM 5 physical address DEFINITION 5 In computing, a physical address, also real address, or binary address, is the memory address that is electronically (in the form of binary number) presented on the computer address bus circuitry in order to enable the data bus to access a particular storage cell of main memory. (address seen by the memory unit- that is the one loaded into the memory-address register of the memory) TERM 6 logical address space DEFINITION 6 The set of all logical addresses generated by a program TERM 7 physical address space DEFINITION 7 set of all physical addresses corresponding to these logical addresses TERM 8 memory management unit DEFINITION 8 A memory management unit (MMU), sometimes called paged memory management unit (PMMU), is a computer hardware component responsible for handling accesses to memory requested by the central processing unit (CPU). (run-time mapping from virtual to physical addresses) TERM 9 dynamic loading DEFINITION 9 Dynamic loading is a mechanism by which a computer program can, at runtime, load a library (or other binary) into memory, retrieve the addresses of functions and variables contained in the library, execute those functions or access those variables, and unload the library from memory. TERM 10 static linking DEFINITION 10 system language libraries are treated like any other object module and are combined by the loader into the binary program image. TERM 21 worst-fist solution to dynamic storage allocation DEFINITION 21 Allocate the largest hole. Again, we must search the entire list, unless it is sorted by size. This strategy produces the largest leftover hole, which may be more useful than the smaller leftover hole from a best-fit approach. TERM 22 external fragmentation DEFINITION 22 As processes are loaded and removed from memory, the free memory space is broken into little pieces. External fragmentation exists when there is enough total memory space to satisfy a request, but the available spaces are not contiguous; storage is fragmented into a large number of small holes. TERM 23 50-percent rule DEFINITION 23 Statistical analysis of first fit, for instance, reveals that, even with some optimization, given N allocated blocks, another 0.5 N blocks will be lost to fragmentation. That is, one-third of memory may be unusable! TERM 24 compaction solution to external fragmentation DEFINITION 24 goal is to shuffle the memory contents so as to place all free memory together in one large block. If relocation is static and is done at assembly or load time, compaction cannot be done; compaction is possible only if relocation is dynamic and is done at execution time. TERM 25 paging DEFINITION 25 memory-management scheme that permits the physical address space of a process to be noncontiguous. Paging avoids the considerable problem of fitting memory chunks of varying sizes onto the backing store; TERM 26 translation look-aside buffer (TLB) DEFINITION 26 The TLBis associative, high-speed memory. Each entry in the TLB consists of two parts: a key (or tag) and a value. When the associative memory is presented with an item, the item is compared with all keys simultaneously. If the item is found, the corresponding value field is returned. The search is fast; the hardware, however, is expensive. Typically, the number of entries in a TLB is small, often numbering between 64 and 1,024. TERM 27 TLB miss DEFINITION 27 page number is not in the TLB TERM 28 wired down DEFINITION 28 TLB entries cannot be removed from the TLB. TERM 29 address space identities DEFINITION 29 An ASID uniquely identifies each process and is Llsed to provide address-space protection for that process. TERM 30 hit ratio DEFINITION 30 percentage of times that a particular page number is found in the TLB TERM 31 effective memory-access time DEFINITION 31 hit ratio+TLB searching+memory access if page number isn't found in TLB then TLB searching+memory access+byte code access TERM 32 valid-invalid DEFINITION 32 When this bit is set to "valid," the associated page is in the process's logical address space and is thus a legal (or valid) page. When the bit is set to"invalid," the page is not in the process's logical address space. Illegal addresses are trapped by use of the valid -invalid bit. The operating system sets this bit for each page to allow or disallow access to the page TERM 33 page-table length register (PTLR) DEFINITION 33 indicates the size of the page table TERM 34 reentrant code (or pure code) DEFINITION 34 cant be shared TERM 35 forward mapped page table DEFINITION 35 address translation works from the outer page table inward
Docsity logo



Copyright © 2024 Ladybird Srl - Via Leonardo da Vinci 16, 10126, Torino, Italy - VAT 10816460017 - All rights reserved