Test 4 with Solutions for Introduction to Computer Engineering | ECE 2030, Exams of Electrical and Electronics Engineering

Download Test 4 with Solutions for Introduction to Computer Engineering | ECE 2030 and more Exams Electrical and Electronics Engineering in PDF only on Docsity! Georgia Institute of Technology ECE 2030G: Introduction to Computer Engineering Instructor: Mike Reid Fall Semester 2001 Test 4 Friday, November 30, 2001 Soturions Name: ne Tce Directions: Four 8 1/2” x 11” pages of notes are altowed (front and back). Calculators are not allowed Verify that you have 5 pages. In order to get full or partial credit, you must show ail of your work. Please make your answers clear and obvious. If] can’t determine your answer or | can’t read your handwriting, then you won't get credit. © Please ask me if you need clarification with a problem Good Luck! Problem Points | Grade “Tesr ] Ditribhoa 1 20 2 10 : Jo's [Oo 3 20 | ) Bo's nl 4 25 ' : Ped Jos 44 Total 100 b | Go's 10 Test 3 73 Z 6 oO Y Test 2 82 Test t ~ 63 . Homework Average : Bl “| H igh 99 Course Average 16 "| a) u 7 Course Grade | Averag 2 1% Problem 1, (20 points) Test 1/2/3 Material la, (10 points) Draw a state diagram for a base-3 sequence recognizer (i.¢., the inputs can be 0, 1, or 2) that outputs a | if the sequences 210 or 00 (i.e., the sequence 2 then | then 0 OR the sequence 0 then 0) are found, Overlapping sequences are allowed. Minimize the number of states. ° A vera connor mispke waste make 2 shes . 1% Store » . “a 1b. (10 points) Implement a half adder circuit using one 1:4 demultiplexer and any additional circuitry necessary (but minimize the design}. Use X and Y for the inputs and S (sum) and CO'( out) for the outputs. “frase outputs must be x Y¥ OR ed efhas » See Test 4) Probie YC HA or an. nplemestaction oF ce q A Fan cton Wb a => te J) 5 demu tfieger ly? CoO Problem 2. (10 points) Single Cycle Datapath - Write the microcode for the following two operations. Be sure to leave space to indicate where one problem ends and the next problem begins. Any register can be modified except register RO which is always 0 Minimize the number of operations. Operation 1 (5 points) - R3 = R7 NAND R1 Hache R4= R3- RY hia Operation 2 (5 points) — R4 = 32 * (R3 ~ R2) RY = R4 ask S {eft Step xX ¥ Zz rwe imm | imva | auen | G/y ju en en oo - moon let shift by 5 => Problem 5. (25 points) Datapath Elements 5a. (5 points) A register file with 1,024 register cells has a bus width of 16 bits. How many registers does the register file Spm in? at of HorceLl _ 2'° Regier (ede cel batloidtn 24 File e~ bus width = cebh /renier = #oF fern =2°=by . jJe- sivale ier ’ 5b. (10 points) Suppose you warié to complement (i.e., toggle) bits 0 and 6 in the 8-bit operand A using the logical unit shown below (all other bits in A stay the same). What does operand B need to be in both binary and hexidecimat notation? What logical function needs to be used? We Fre XoR functor te Complement bits selectively. t3p- 4 Aap—A Af-bematively 5 B=BBB.B,B,BB,B,-_OlOO O00] = Ox4| loll (10 = OxBE (give answer in both binary and hexidecimal notation) LFSLFLFLPLR=____ OL |O._ > Xok_Functina [001 > XAR Sc. (10 points) Beginning with the incomplete circuit below, compiete the design for a 4-bit logical shifter that can shift two bits left or right. Label the data inputs as Ip, Ih, Ih, Is, and the control input as Right |Left. The outputs are already labeled as Oo, Oj, O2, and Os o 4; L o q, XS oO r, t ° nyt | Wh - pot) 01 it» [EE no] oe Stadt: TF —2 aur L-bit [eft loyal shit [LT 00 | nll, 3LTR ti 2 td it oor,tT, Subscript O % aluons tre LSB. The hight subscript (3) is ee ree ane he Bf en apt PH 96 96 96 95 94 92 a1 90 Final Exam Breakdown Combinational Logic AB 88 88 88 Sequential Logic Architecture B 87 86 86 86 86 85 85 82 82 81 81 81 80 80 ECE 2030G Class Averages after Test 4 B-c 78 c 76 76 D F 69 52 68 50 68 41 67 15 67 1 66 66 66 A 11 15 B 18 15 c 12 11 D 8 8 F 5 5 Avg 2.41 2.50 4g 3x8 8