Three Pillars of Computer Architecture-Advance Computer Architecture-Lecture Slides, Slides of Advanced Computer Architecture

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Today‟s Topics Recap ISA Taxonomy Memory Addressing modes Types of operands Types of operations Summary docsity.com Recap: Lec. 1-3 Chapter 1 Computer design cycle Performance metrics: Processor and I/O systems Price-Performance design Benchmarks: Performance evaluation Quantitative principles: Performance enhancement docsity.com Changing Definitions of Computer Architecture … Cont‟d 1990s to date: The focus of the Computer Architecture Course is the Design of CPU, memory system, I/O system, Multiprocessors based on the quantitative principles to have price - performance design; i.e., maximum performance at minimum price docsity.com Instruction Set Architecture – ISA instruction set software hardware Our focus in couple of lectures will be the Instruction Set Architecture – ISA which is the interface between the hardware-software It plays a vital role in understanding the computer architecture from any of the above mentioned perspectives docsity.com Instruction Set Architecture – ISA instruction set software hardware The design of hardware and software can‟t be initiated without defining ISA It describes the instruction word format and identifies the memory addressing for data manipulation and control operations docsity.com Taxonomy of Instruction Set ….. Cont’d Basic Differentiator: The type of internal storage of the operand Major Choices of ISA: – Stack Architecture: – Accumulator Architecture – General Purpose Register Architecture  Register – memory  Register – Register (load/store)  Memory – Memory Architecture (Obsolete) docsity.com Stack Architecture Both the operands are implicitly on the TOS Thus, it is also referred to as Zero-Address machine The operand may be either an input (orange shade) or result from the ALU (yellow shade) All operands are implicit (implied or inherited) The first operand is removed from the stack and the second operand is replaced by the result TOS ALU Processor Memory . . . . . . . . docsity.com Stack Architecture TOS ALU To execute: C=A+B ADD instruction has implicit operands for the stack – operands are written in the stack using PUSH instruction PUSH A PUSH B ADD POP C docsity.com General Purpose Register Architecture Many general purpose registers are available within CPU Generally, CPU registers do not have dedicated functions and can be used for a variety of purposes – address, data and control A relatively small number of bits in the instruction is needed to identify the register In addition to the GPRs, there are many dedicated or special-purpose registers as well, but many of them are not “visible” to the programmer GPR architecture has explicit operands either in register or memory thus there may exist: - Register – memory architecture - Register – Register (Load/Store) Architecture - Memory – Memory Architecture Processor docsity.com General Purpose Register Architecture One explicit operand is in a register and one in memory and the result goes into the register The operand in memory is accessed directly To execute: C=A+B ADD instruction has explicit operand A loaded in a register and the operand B is in memory and the result is in register Load R1, A ADD R3, R1, B Store R3, C Register – Memory Architecture R1 ALU Memory . . . . . . . . R3 R2 . . . . . . . . Processor docsity.com General Purpose Register Architecture The explicit operands in memory are first loaded into registers temporarily and Are transferred to memory by Store instruction To execute: C=A+B ADD instruction has implicit operands A and B loaded in registers Load R1, A Load R2, B ADD R3, R1, R2 Store R3, C Both the explicit operands are not accessed from memory directly, i.e., Memory – Memory Architecture is obsolete Register – Register (Load/store) Architecture R1 ALU Memory . . . . . . . . R3 . . . . . . . . Processor R2 docsity.com Comparison of three GPR Architectures Memory- Memory Advantages Most compact Doesn‟t waste registers for temporary storages Disadvantages Large variation in instruction size Large variation in work per instruction Memory bottleneck by memory access docsity.com Evolution of Instruction Sets Single Accumulator (EDSAC 1950) Accumulator + Index Registers (Manchester Mark I, IBM 700 series 1953) Separation of Programming Model from Implementation 1963-64 High-level Language Based (B5000 1963) Concept of a Family (IBM 360 1964) General Purpose Register Machines Complex Instruction Sets Computer (Vax, Intel 432 1977-80) Load/Store Architecture Reduced Instruction Set Computer (Mips,Sparc,HP-PA,IBM RS6000, . . .1987) (CDC 6600, Cray 1 1963-76) docsity.com Types and Size of Operands Types of an Operand - Integer - Single-precision floating point - Character Size of Operand - Character 8-bit - Half word 16-bit - Single precision FP or Word 32-bit - Double precision FP or 64-bit double word docsity.com Operand Addressing Modes An “effective address” is the binary bit pattern issued by the CPU to specify the location of operands in CPU (register) or the memory Addressing modes are the ways of providing access paths to CPU registers and memory locations Commonly used addressing modes are: - Immediate - Register - Direct or Absolute - Indirect docsity.com Operand Addressing Modes - Immediate ADD R4, # 24H Reg[R4] Reg[R4] + 24 H Data for the instruction is part of the instruction itself Used to hold source operands only; cannot be used for storing results - Register ADD R4, R3 Reg[R4] Reg[R4] + Reg[R3] Operand is contained in a CPU register No memory access needed , therefore it is fast - Direct (or absolute) ADD R1,(1000) Reg[R1] Reg[R1] + Mem[1000] The address of the operand is specified as a constant, coded as part of the instruction Limited address space (2operand field size) locations docsity.com Commonly used addressing modes … cont‟d Indirect Addressing modes The address of the memory location where the data is to be found is stored in the instruction as the operand, i.e., the operand is the address of an address Large address space ( 2 memory word size) available Two or more memory accesses are required docsity.com Special Addressing Modes Used for stepping within loops; R2 points to the start of the array; each reference increments / decrements R2 by „d‟; the size of the elements in the array - Auto-increment ADD R1, (R2)+ (i) Reg[R1] Reg[R1] + Mem[Reg [R2]] (ii) Reg[R2] Reg[R2] + d - Auto-decrement ADD R1, (R2)- (i) Reg[R2] Reg[R2] - d (ii) Reg[R1] Reg[R1] + Mem[Reg [R2]] - Scaled ADD R1, 100(R2)[R3] Reg[R1] Reg[R1] + Mem[100+Reg [R2] + R3]*d] docsity.com Addressing Modes of Control Flow Instructions - Branch (conditional) a sort of displacement, in number of instructions, relative to PC - Jump (Unconditional) jump to an absolute address, independent of the position of PC - Procedure call/return control transfer with some state and return address saving, some times in a special link register or in some GPRs docsity.com Summary ISA Taxonomy – Stack Architecture: – Accumulator Architecture – General Purpose Register Architecture  Register – memory  Register – Register (load/store)  Memory – Memory Architecture (Obsolete) docsity.com