RTL Functional Verification using TL Modeling, TL Test Bench, and Hardware Emulation, Exams of Spanish Language

Download RTL Functional Verification using TL Modeling, TL Test Bench, and Hardware Emulation and more Exams Spanish Language in PDF only on Docsity! Transaction Level (TL) Modeling of SoC & Functional Verification of RTL reusing TL Test Bench and HW Emulation ECE 255B Arup De Prof. Li-C. Wang Content Introductioni Transaction Level (TL) Modelingi l li Functional Verification i l i i i Hardware Emulation l i Hardware Assisted TL Test Bench for RTL i Experimenti Conclusionsl i Introduction
Motivation
Increase effort in SoC embedded software development
Increase effort in architectural exploration
Increase Time-to-market pressure
Increase cost Classical Design Flow Classical Design Flow System Specification HW Development SW Development Prototype Chip Fabrication System Integration System Validation HW Re-design SW Re-design No communication Novel Design Flow System Specification HW/SW Partitioning TLM HW Development SW Development Prototype System Integration & Validation Chip Fabrication Concurrent HW & SW Engineering Novel Design Flow Transaction Level Modeling
What is TLM?
High level modeling approach for digital systems
Communication among modules are separated from the implementation of functional units
Communication uses function calls burst_read(char* buf, int addr, int len);
Language used: SystemC Transaction Level Modeling RTL RTL Pin Accurate Functional model Functional model Function Call Simulate every event 100-10000x faster Write(address,data) Transaction Level Modeling
SystemC is …
C++ Class Library extensively used for TLM models for digital systems
Provides hardware constructs
Notion of Time
Concurrency
HW data types(tri-state ’z’, don’t-care ’x’)
Supports different levels of abstraction (PV, PVT, CA etc.)
Further information: www.systemc.org Transaction Level Modeling
Port : object through which a module can access a channel’s interface. Primitive channel Hierarchical channel a Transaction Level Modeling your standard Cic++ development environment class library and source files for system simulation kernel and test benches "make" tale, meer "Kon epenttic® executable = simulator — = as = = SystemC environment Transaction Level Modeling
Why is TLM interesting?
Fast and compact
Integrate HW and SW models
Early platform for SW development
Early system exploration and verification
Verification reuse Functional Verification
Different approaches
Black Box: Functionality is known but only access to input/output port
Ideal but takes long simulation time
White Box: Internal structure is completely visible & utilized for simulation and checking
Small simulation time but inflexible if design changes
Grey Box: limited internal structure access
Most commonly used
Combines flexibility and small simulation time Test Bench Base Objects Test Generation Test Case Driver DUT Input Monitor Checker/ scoreboard Output Monitor Test Bench Architecture Pass/Fail Specman Elite Constraint-driven Test Generation Functional Coverage Analysis Data & Temporal Checking Commercial HDL Simulator HDL Legacy Code (C, HDL) - Verification Environment - Reference Models - Tests Interface Specification and Functional Test Plan - e HW Emulation
Use Models
Self-Test bench Emulation
Both synthesizable TB and DUT run on emulator at high frequency(1-10MHz)
Cycle Accurate Co-Emulation
TB run on work station and DUT on emulator
Low frequency(1-5 KHz)
Interface signals update at each clock cycle
Transactional Co-Emulation
Same as CA except interface signals are exchange during communication only not every clock cycle
Frequency (10-100KHz) Content Introductioni Transaction Level (TL) Modelingi l li Functional Verification i l i i i Hardware Emulation l i Hardware Assisted TL Test Bench for RTL i Resultsl Conclusionsl i Reuse TL Test Bench
Reuse TL Test Bench for RTL Models
Reduce development time and cost
Requires transactors
Maps TLM function calls to RTL signals and vice versa
Use HW emulation technique to improve simulation speed Transactor(cont.) SW Transactor HW TransactorInterface to TLM TB Interface to RTL DUT Transactor SystemC- Verilog Interface SystemC Verilog Architecture SystemC- Verilog Interface SW Transactor TLM TB HW Transactor DUT (Verilog) Transaction Specific Interface Signal Level Interface SW side: SystemC HW side: Verilog FPGA Content Introductioni Transaction Level (TL) Modelingi l li Functional Verification i l i i i Hardware Emulation l i Hardware Assisted TL Test Bench for RTL i Experimenti Conclusionsl i SPIC
Consists of 4 registers:
Edge Enable Register
Polarity Register
Mask Register
Pending Register Waveform A: Waveform at Transaction Level B: Waveform at RTL Level (1) (2) (3) Results & Observation 9.24852,299.121.1359,098Hardware acc. 15,655.3110.4559,098Mixed-level Sim. SpeedupCycles/secTime(sec)Simulation Cycle Table: Hardware Acceleration speedup result for JPEG decoder
Comparison of TLM and RTL simulation speed for SDRAM controller
RTL: 2.9 kcycles/sec
TLM: 44.5 kcycles/sec