Transistor Amplifier - Introduction to Microelectronic Circuits - Solved Exam, Exams of Microelectronic Circuits

Download Transistor Amplifier - Introduction to Microelectronic Circuits - Solved Exam and more Exams Microelectronic Circuits in PDF only on Docsity! EECS40 Final Exam | SOLUTIONS Spring 2000 Problem 1: Circuit Analysis [35 points] a) Find V,.. [5 pts] + 3kQ 10ma (|) Vy, Oey Source tran sformacion i | V,=_=-6 Vv 1OmA ® ig ZmA 28 mA b. i 0.15 k Vg = € 8mh)(0:75kR.) = 46V L b) In the circuit below, the independent source values and resistances are known. Use the nodal analysis technique to write 2 equations sufficient to solve for v, and vy. To receive credit, you must write your answer in the box below. [10 pts] Apply Kel to supernode : 100k, | Vo ~ Vy Y . Vy liad s+ 44, - s=0 R, Ro Ry Write the nodal equations here: Need +o write touehons wh, ealy Vx Ruy as : Unknowns Van - Vx Vx Ve Be Ree 100 A Oe Vee = Vx- Uy 3 of 16 EECS40 Final Exam Spring 2000 Problem 1 (continued) ¢) Consider the following circuit: 1kQ y SKQ y 11kO : i) Find the numerical value of y,. [5 pts] Apply KCL to node Xi ~ VE L ff V~- Ux ~V~ Ue ka ~ jokn Sen 40-10%% -V_ + 20Vz =O => -9% 2 90 =P UZ F- IOV ii) Find the power development/absorbed by the dependent source. [5 pts} Current ty Ftowing Through dependent source > is equal fo currént Frowing Through S kA resishr Gece) =- - ‘ developed, absorbes js Ve - % _ Uri _ idus < loov {circle correct choice) 4 SER Ska ~ Fea” Sen * 20mA power absorbed = ryly = CHOV)(20mA) = -2200mW > power is devehped | iii) Draw the Thevenin Equivalent Circuit. [6 pts] Shorting derminals a and b together ‘ Thevenin Equivalent Circuit: SR D> ity a Ase" ka b = lwov WkED NM “= 10mA P Noe _ uke) The oxpors ND iv) What is the maximum power that can be delivered to a load resistor R; connected between terminals a and b? [4 pts] (2h, = 2 = 27S mW 4 of 16 EECS40 Final Exam Spring 2000 Problem 3: Transient Response [35 points] a) In the circuit below, the switch is at position 1 for a long time and is then moved to position 2 at t=0. Ry R 1 x 2 y . av, For t<o, Ww \WW—4 te, = C Fy =¢ 4% be2 & a Vy = Vy= Vi © bd C; te] —— & i) Write 2 independent differential equations relating V, and Vs for ¢> 0. To receive credit, you must write your answer in the box below.[8 pts] . Vy AUK | Uy % . Applyvag KCL to noden: Bt at oo. O (Equation ) . Vy - Vy Av; : , JT EX 4 App lying KCL 4. node 4! BQ + Co AE = oO (Equation 2) Write the differential equations here: Av x toy V% Cae + late) ~ a 20 4% Me — aw tm @zO ° dv ii) At what rate does V,, change (ie, what is a Jat r = 07? [4 pts] At tro, Ux = Vy = V, Since voltages across V, Capacrtors Cannod change instantaneously, dv, zc co a RM dp ~—SE— beg a =O = We za *7 Se Cc iif) At what rate does V,, change at = 0*? {3 pts] KC! dvy { From Equation | yO de 7 He, y-%) =O 4 7 of 16 EECS40 Final Exam Spring 2000 Problem 3 (continued) b) In the circuit below, the switch has been in the closed position for a long time. The switch is opened at ¢ = 0, and then closed again at. ¢ = 0.5 ns. . P 6 With switch closed, div inductor “sees” oe 3kQ Fr t<o, dt =0 —A\\—¥ - + ZBeM resistor tn pace 2 ¥=0 + with 6 ka resishr: = 36) 50 6kn vesishy §=8V eS U 2H 6.0F YR Reg Fre 2 kKD is shorted out bv i G(to)= Foam i) Write an equation for i, (t) for 0 <t<0.5ns [8 pts] 2uh 3 Ff bkn. i (ot)= y (0-) =2QmA TF switch, were te stay oper indehnitely, the bn vahe of t, would be 0, G(t)= Final value + (inihal vebee - Bred Value) e-th-) ' — 3x 107+ Equation for i;: alt) & e mA : O<t<O.Sns - (3x107) 0.510") ii) Write an equation for i, (t) for t>0.5ns.[8pts]) At £7 O.5ns~ eae hs ty losast) = 6 (0,Snst) = 0045 mA = 20°" = 0,45 Final valuc of ty (switch closed) is oe &. perare 4 ilt)2 2+ (0.451 - 2) | nlt OSes )MH/ke) Reg= 2x108 = 19'S : -/07 (€ -%5ns) Equation for i;: a-1,55¢ moe mA t> 0.5ns iii) Neatly sketch i, (¢) on the axes provided. [4 pts] i,(mA) BR timeconstant = “5 i \ \ > t(ns) 8 of 16 -EECS40 Final Exam Spring 2000 Problem 4: p-n Junctions; Diodes (25 points] ‘a) Consider a p-n junction of area 1 jm? formed in a p-type silicon sample maintained at 300K. The p and n regions are uniformly doped, as indicated in the figure below. n-type: Np-Na = 107° cm? 0.5 um DUA “vt p-type: Na = 1017 cm? Schematic cross-sectional view of p-n junction “i) What is the sheet resistance of the n-type region? [9 pts] n-type region + NM? No-Ny = 10%em™? >> p R= { 5.6 QO/square + gene grep team Evom plot of mobility vs. Aopant concentration on Page2, fn * 80 on®/Vs foe yt Ny = 102m ge r = paant = [422x707 io 102? )(o.sxi0+)] = 15,6 2/o ii) What is the junction capacitance? (Consider the worst case: 0V bias voltage.) [10 pts] for = Ty Wormer) | built-in poten Pee > go bn Poo = 0.99V Zs (Arvo pp _ [Rex saree em) L _ J gM) = a ioe t den) = 011m " . “lt Es; 2 Una) (B.3syxto') “I A Ka = (10°) hiss = FTX & a] 9 of 16 EECS40 Final Exam Spring 2000 Problem 6: CMOS Circuit [30 points] The layout of a CMOS circuit is shown below: yrwel n-well z Contact Vop (7 n-well (dark) [B) oxide (dark) I gate (clear) <2 select (dark . and clear) nt | N2 a) : io oe X] contact (dark) GND (a) Mf ea] Peal GND metal (clear) Said cnc ac acacia Ga aa pecan PHOS transishors: fl, PZ le p-substrate contact NMOS transistors + Ni,N2, N3, Ny — PItNI orm one inverters p22 Be, another snvertte The following fabrication process (starting with a p-type Si wafer) is used: 1. Thermally grow 700 nm of SiO. 2. Pattern the SiO, using the well mask. 3. Implant phosphorus and perform a high-temperature, long anneal to "drive in" the well to a depth of 2 um. 4. Remove the SiO, (using a highly selective wet etch process, which does not etch Si). 5. Grow 500 nm of SiO, ("field oxide"). 6. Pattern the SiO, using the oxide (“active-area”) mask. 7. Thermally grow 10 nm of SiO, ("gate oxide") in the bare regions of the Si. 8. Deposit 500 nm of heavily doped poly-Si (by CVD). 9. Pattern the poly-Si using the gate mask. 10. Use dark-field select mask to pattern photoresist; implant boron; strip the photoresist. This will form the p+ source and drain junctions for the p-channel MOSFET. 11. Use clear-field select mask to pattern photoresist; implant arsenic; strip the photoresist. This will form the n+ source and drain junctions for the n-channel MOSFET. 12. Anneal the wafer in order to activate the dopants. The final source/drain junction depth is 250 nm. 13. Deposit 500 nm of SiO} ("passivation oxide"). 14. Pattern the deposited SiO, film using the contact mask. 15. Deposit 750 nm of aluminum. 16. Pattern the Al using the metal mask. 12 of 16 EECS40 Final Exam Spring 2000 Problem 6 (continued) a) Draw cross-section A-A’ in the space provided. Identify all layers clearly. [15 pts] 7 passivation § tessiva,» a 3 poly-Si \'e Fide_) Field Oxide } passivation S/D2 Tope ae n-well Si substrate (p-type) Cross-section A-A’ b) Draw cross-section C-C’ in the space provided. Identify all layers clearly. [10 pts] passivation 5:9, aisiebon te AT passivation SiO. Feld St. [ field Sid, { Bald Sie, ay t ir Si Substrate Cross-section C-C’ ) Draw the circuit schematic, labelling Vpp, GND, W, B and B. [5 pts} Circuit schematic 13 of 16 EECS40 Final Exam Spring 2000 Problem 7: Logic Circuit; Gate Delay Analysis [30 points] Consider the following logic circuit: A— Cc 1 Eat 5 Ps : > EFF fox (2.9) (9.95¥x 107") Sa Ee 2 ton 25%)077 1) 38aF om The NAND gate circuit schematic is given below: Vpp ae aes ae ee /L = 0.3 wm/0.2 um Your Ry = 20kQ Yni—| NMOs: WIL = 0.2 pm/0.2 pm R, = 10kQ Vy a Worst case pull-up [only one PMOSFET ON ) resistance a pull-down resistance = ROkL a) Fill out the truth table, and write a simple logical expression for the function G. [5 pts] Gate-oxide thickness = 2.5 nm A B Be ap a NAND Truth Table : i B Cc D E F G ; i Z ae 0 Oalet | | O Ono || Bl 0 1 0 2) ) | 0 | I 1 0 0 | oO | le 0 me 1 1 0 0 | | 0 c= 46+ BA (exclusive OR) 14 of 16